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Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples

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This commit is contained in:
stefandesouza
2024-02-24 21:03:15 +01:00
parent dcfe36b850
commit d858827a47
3 changed files with 56 additions and 66 deletions
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12
osaca/parser/memory.py
View File

@@ -15,7 +15,6 @@ class MemoryOperand(Operand):
pre_indexed=False,
post_indexed=False,
indexed_val=None,
port_pressure=[],
dst=None,
source=False,
destination=False,
@@ -30,7 +29,6 @@ class MemoryOperand(Operand):
self._pre_indexed = pre_indexed
self._post_indexed = post_indexed
self._indexed_val = indexed_val
self._port_pressure = port_pressure
self._dst = dst
@property
@@ -73,10 +71,6 @@ class MemoryOperand(Operand):
def indexed_val(self):
return self._indexed_val
@property
def port_pressure(self):
return self._port_pressure
@property
def dst(self):
return self._dst
@@ -85,10 +79,6 @@ class MemoryOperand(Operand):
def dst(self, dst):
self._dst = dst
@port_pressure.setter
def port_pressure(self, port_pressure):
self._port_pressure = port_pressure
@segment_ext.setter
def segment_ext(self, segment):
self._segment_ext = segment
@@ -131,7 +121,7 @@ class MemoryOperand(Operand):
f"base={self._base}, index={self._index}, scale={self._scale}, "
f"segment_ext={self._segment_ext}, mask={self._mask}, "
f"pre_indexed={self._pre_indexed}, post_indexed={self._post_indexed}, "
f"indexed_val={self._indexed_val}, port_pressure={self._port_pressure}),"
f"indexed_val={self._indexed_val},"
f"source={self._source}, destination={self._destination})"
)

33
osaca/semantics/hw_model.py
View File

@@ -47,7 +47,6 @@ class MachineModel(object):
"index": i,
"offset": o,
"scale": s,
"port_pressure": [],
}
for b, i, o, s in product(["gpr"], ["gpr", None], ["imd", None], [1, 8])
],
@@ -150,29 +149,29 @@ class MachineModel(object):
new_throughputs = []
if "load_throughput" in self._data:
for m in self._data["load_throughput"]:
new_throughputs.append(
new_throughputs.append((
MemoryOperand(
base=m["base"],
offset=m["offset"],
scale=m["scale"],
index=m["index"],
port_pressure=m["port_pressure"],
dst=m["dst"] if "dst" in m else None,
)
, m["port_pressure"])
)
self._data["load_throughput"] = new_throughputs
new_throughputs = []
if "store_throughput" in self._data:
for m in self._data["store_throughput"]:
new_throughputs.append(
new_throughputs.append((
MemoryOperand(
base=m["base"],
offset=m["offset"],
scale=m["scale"],
index=m["index"],
port_pressure=m["port_pressure"],
)
, m["port_pressure"])
)
self._data["store_throughput"] = new_throughputs
@@ -309,7 +308,7 @@ class MachineModel(object):
def set_instruction(
self,
instruction,
mnemonic,
operands=None,
latency=None,
port_pressure=None,
@@ -318,13 +317,13 @@ class MachineModel(object):
):
"""Import instruction form information."""
# If it already exists. Overwrite information.
instr_data = self.get_instruction(instruction, operands)
instr_data = self.get_instruction(mnemonic, operands)
if instr_data is None:
instr_data = InstructionForm()
self._data["instruction_forms"].append(instr_data)
self._data["instruction_forms_dict"][instruction].append(instr_data)
self._data["instruction_forms_dict"][mnemonic].append(instr_data)
instr_data.instruction = instruction
instr_data.mnemonic = mnemonic
instr_data.operands = operands
instr_data.latency = latency
instr_data.port_pressure = port_pressure
@@ -333,10 +332,10 @@ class MachineModel(object):
def set_instruction_entry(self, entry):
"""Import instruction as entry object form information."""
if entry.instruction is None and entry.operands == []:
if entry.mnemonic is None and entry.operands == []:
raise KeyError
self.set_instruction(
entry.instruction,
entry.mnemonic,
entry.operands,
entry.latency,
entry.port_pressure,
@@ -373,10 +372,10 @@ class MachineModel(object):
def get_load_throughput(self, memory):
"""Return load thorughput for given register type."""
ld_tp = [m for m in self._data["load_throughput"] if self._match_mem_entries(memory, m)]
ld_tp = [m for m in self._data["load_throughput"] if self._match_mem_entries(memory, m[0])]
if len(ld_tp) > 0:
return ld_tp.copy()
return [MemoryOperand(port_pressure=self._data["load_throughput_default"].copy())]
return (memory, self._data["load_throughput_default"].copy())
def get_store_latency(self, reg_type):
"""Return store latency for given register type."""
@@ -385,16 +384,16 @@ class MachineModel(object):
def get_store_throughput(self, memory, src_reg=None):
"""Return store throughput for a given destination and register type."""
st_tp = [m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m)]
st_tp = [m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m[0])]
if src_reg is not None:
st_tp = [
tp
for tp in st_tp
if "src" in tp and self._check_operands(src_reg, RegisterOperand(name=tp["src"]))
if "src" in tp[0] and self._check_operands(src_reg, RegisterOperand(name=tp[0]["src"]))
]
if len(st_tp) > 0:
return st_tp.copy()
return [MemoryOperand(port_pressure=self._data["store_throughput_default"].copy())]
return [(memory, self._data["store_throughput_default"].copy())]
def _match_mem_entries(self, mem, i_mem):
"""Check if memory addressing ``mem`` and ``i_mem`` are of the same type."""
@@ -422,7 +421,7 @@ class MachineModel(object):
if op.shape is not None:
op_attrs.append("shape:" + op.shape)
operands.append("{}({})".format("register", ",".join(op_attrs)))
return "{} {}".format(instruction_form.instruction.lower(), ",".join(operands))
return "{} {}".format(instruction_form.mnemonic.lower(), ",".join(operands))
@staticmethod
def get_isa_for_arch(arch):

77
tests/test_semantics.py
View File

@@ -160,9 +160,9 @@ class TestSemanticTools(unittest.TestCase):
)
name_arm_1 = "fadd"
operands_arm_1 = [
RegisterOperand(prefix_id="v", shape="s"),
RegisterOperand(prefix_id="v", shape="s"),
RegisterOperand(prefix_id="v", shape="s"),
RegisterOperand(prefix="v", shape="s"),
RegisterOperand(prefix="v", shape="s"),
RegisterOperand(prefix="v", shape="s"),
]
instr_form_arm_1 = test_mm_arm.get_instruction(name_arm_1, operands_arm_1)
self.assertEqual(instr_form_arm_1, test_mm_arm.get_instruction(name_arm_1, operands_arm_1))
@@ -190,52 +190,53 @@ class TestSemanticTools(unittest.TestCase):
self.assertEqual(
test_mm_x86.get_store_throughput(
MemoryOperand(
base_id=RegisterOperand(name="x"), offset_ID=None, index_id=None, scale_id=1
base=RegisterOperand(name="x"), offset=None, index=None, scale=1
)
)[0].port_pressure,
)[0][1],
[[2, "237"], [2, "4"]],
)
self.assertEqual(
test_mm_x86.get_store_throughput(
MemoryOperand(
base_id=RegisterOperand(prefix_id="NOT_IN_DB"),
offset_ID=None,
index_id="NOT_NONE",
scale_id=1,
base=RegisterOperand(prefix="NOT_IN_DB"),
offset=None,
index="NOT_NONE",
scale=1,
)
)[0].port_pressure,
)[0][1],
[[1, "23"], [1, "4"]],
)
self.assertEqual(
test_mm_arm.get_store_throughput(
MemoryOperand(
base_id=RegisterOperand(prefix_id="x"),
offset_ID=None,
index_id=None,
scale_id=1,
base=RegisterOperand(prefix="x"),
offset=None,
index=None,
scale=1,
)
)[0].port_pressure,
)[0][1],
[[2, "34"], [2, "5"]],
)
self.assertEqual(
test_mm_arm.get_store_throughput(
MemoryOperand(
base_id=RegisterOperand(prefix_id="NOT_IN_DB"),
offset_ID=None,
index_id=None,
scale_id=1,
base=RegisterOperand(prefix="NOT_IN_DB"),
offset=None,
index=None,
scale=1,
)
)[0].port_pressure,
)[0][1],
[[1, "34"], [1, "5"]],
)
# test get_store_lt
self.assertEqual(
test_mm_x86.get_store_latency(
MemoryOperand(
base_id=RegisterOperand(name="x"), offset_ID=None, index_id=None, scale_id=1
base=RegisterOperand(name="x"), offset=None, index=None, scale=1
)
),
0,
@@ -243,10 +244,10 @@ class TestSemanticTools(unittest.TestCase):
self.assertEqual(
test_mm_arm.get_store_latency(
MemoryOperand(
base_id=RegisterOperand(prefix_id="x"),
offset_ID=None,
index_id=None,
scale_id=1,
base=RegisterOperand(prefix="x"),
offset=None,
index=None,
scale=1,
)
),
0,
@@ -259,9 +260,9 @@ class TestSemanticTools(unittest.TestCase):
self.assertEqual(
test_mm_x86.get_load_throughput(
MemoryOperand(
base_id=RegisterOperand(name="x"), offset_ID=None, index_id=None, scale_id=1
base=RegisterOperand(name="x"), offset=None, index=None, scale=1
)
)[0].port_pressure,
)[0][1],
[[1, "23"], [1, ["2D", "3D"]]],
)
@@ -604,11 +605,11 @@ class TestSemanticTools(unittest.TestCase):
def test_is_read_is_written_AArch64(self):
# independent form HW model
dag = KernelDG(self.kernel_AArch64, self.parser_AArch64, None, None)
reg_x1 = RegisterOperand(prefix_id="x", name="1")
reg_w1 = RegisterOperand(prefix_id="w", name="1")
reg_d1 = RegisterOperand(prefix_id="d", name="1")
reg_q1 = RegisterOperand(prefix_id="q", name="1")
reg_v1 = RegisterOperand(prefix_id="v", name="1", lanes="2", shape="d")
reg_x1 = RegisterOperand(prefix="x", name="1")
reg_w1 = RegisterOperand(prefix="w", name="1")
reg_d1 = RegisterOperand(prefix="d", name="1")
reg_q1 = RegisterOperand(prefix="q", name="1")
reg_v1 = RegisterOperand(prefix="v", name="1", lanes="2", shape="d")
regs = [reg_d1, reg_q1, reg_v1]
regs_gp = [reg_w1, reg_x1]
@@ -674,10 +675,10 @@ class TestSemanticTools(unittest.TestCase):
def test_MachineModel_getter(self):
sample_operands = [
MemoryOperand(
offset_ID=None,
base_id=RegisterOperand(name="r12"),
index_id=RegisterOperand(name="rcx"),
scale_id=8,
offset=None,
base=RegisterOperand(name="r12"),
index=RegisterOperand(name="rcx"),
scale=8,
)
]
self.assertIsNone(self.machine_model_csx.get_instruction("GETRESULT", sample_operands))