mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-04 18:20:09 +01:00
removed unused DBs
This commit is contained in:
JanLJL
@@ -1,14 +0,0 @@
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#!/usr/bin/env python3
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from osaca.parser import ParserAArch64v81, ParserX86ATT
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# from .marker_utils import reduce_to_section
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class Analyzer(object):
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def __init__(self, parser_result, isa):
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self.ISA = isa
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if isa == 'x86':
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self.parser = ParserX86ATT()
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elif isa == 'AArch64':
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self.parser = ParserAArch64v81()
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self.kernel = parser_result
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@@ -1,223 +0,0 @@
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#!/usr/bin/env python3
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from collections import defaultdict, OrderedDict
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import xml.etree.ElementTree as ET
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import re
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import sys
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import argparse
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from distutils.version import StrictVersion
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from osaca.param import Parameter, Register
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from osaca.eu_sched import Scheduler
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def normalize_reg_name(reg_name):
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# strip spaces
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reg_name = reg_name.strip()
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# masks are denoted with curly brackets in uops.info
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reg_name = re.sub(r'{K([0-7])}', r'K\1', reg_name)
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reg_name = re.sub(r'ST\(([0-7])\)', r'ST\1', reg_name)
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return reg_name
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def port_occupancy_from_tag_attributes(attrib, arch):
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occupancy = defaultdict(int)
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for k, v in attrib.items():
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m = re.match('^port([0-9]+)', k)
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if not m:
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continue
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ports = m.group(1)
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# Ignore Port7 on HSW, BDW, SKL and SKX if present in combination with ports 2 and 3.
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# Port7 is only used for simple address generation, while 2 and 3 handle all addressing,
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# but uops.info does not differentiate.
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if arch in ['HSW', 'BDW', 'SKL', 'SKX'] and ports == '237':
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ports = ports.replace('7', '')
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potential_ports = list(ports)
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per_port_occupancy = int(v) / len(potential_ports)
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for pp in potential_ports:
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occupancy[pp] += per_port_occupancy
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# Also consider DIV pipeline
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if 'div_cycles' in attrib:
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occupancy['0DV'] = int(attrib['div_cycles'])
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return dict(occupancy)
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def extract_paramters(instruction_tag):
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# Extract parameter components
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parameters = [] # used to store string representations
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parameter_tags = sorted(instruction_tag.findall("operand"),
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key=lambda p: int(p.attrib['idx']))
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for parameter_tag in parameter_tags:
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# Ignore parameters with suppressed=1
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if int(parameter_tag.attrib.get('suppressed', '0')):
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continue
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p_type = parameter_tag.attrib['type']
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if p_type == 'imm':
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parameters.append('imd') # Parameter('IMD')
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elif p_type == 'mem':
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parameters.append('mem') # Parameter('MEM')
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elif p_type == 'reg':
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possible_regs = [normalize_reg_name(r)
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for r in parameter_tag.text.split(',')]
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reg_groups = [Register.sizes.get(r, None) for r in possible_regs]
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if reg_groups[1:] == reg_groups[:-1]:
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if reg_groups[0] is None:
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raise ValueError("Unknown register type for {} with {}.".format(
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parameter_tag.attrib, parameter_tag.text))
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elif reg_groups[0][1] == 'GPR':
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parameters.append('r{}'.format(reg_groups[0][0]))
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# Register(possible_regs[0]))
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elif '{' in parameter_tag.text:
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# We have a mask
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parameters[-1] += '{opmask}'
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else:
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parameters.append(reg_groups[0][1].lower())
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elif p_type == 'relbr':
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parameters.append('LBL')
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elif p_type == 'agen':
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parameters.append('mem')
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else:
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raise ValueError("Unknown paramter type {}".format(parameter_tag.attrib))
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return parameters
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def extract_model(tree, arch):
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model_data = []
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for instruction_tag in tree.findall('//instruction'):
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ignore = False
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mnemonic = instruction_tag.attrib['asm']
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# Extract parameter components
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try:
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parameters = extract_paramters(instruction_tag)
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except ValueError as e:
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print(e, file=sys.stderr)
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# Extract port occupation, throughput and latency
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port_occupancy, throughput, latency = [], 0.0, None
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arch_tag = instruction_tag.find('architecture[@name="'+arch+'"]')
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if arch_tag is None:
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continue
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# We collect all measurement and IACA information and compare them later
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for measurement_tag in arch_tag.iter('measurement'):
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port_occupancy.append(port_occupancy_from_tag_attributes(measurement_tag.attrib, arch))
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# FIXME handle min/max Latencies ('maxCycles' and 'minCycles')
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latencies = [int(l_tag.attrib['cycles'])
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for l_tag in measurement_tag.iter('latency') if 'latency' in l_tag.attrib]
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if latencies[1:] != latencies[:-1]:
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print("Contradicting latencies found:", mnemonic, file=sys.stderr)
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ignore = True
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elif latencies:
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latency = latencies[0]
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# Ordered by IACA version (newest last)
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for iaca_tag in sorted(arch_tag.iter('IACA'),
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key=lambda i: StrictVersion(i.attrib['version'])):
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port_occupancy.append(port_occupancy_from_tag_attributes(iaca_tag.attrib, arch))
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if ignore: continue
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# Check if all are equal
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if port_occupancy:
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if port_occupancy[1:] != port_occupancy[:-1]:
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print("Contradicting port occupancies, using latest IACA:", mnemonic,
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file=sys.stderr)
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port_occupancy = port_occupancy[-1]
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throughput = max(list(port_occupancy.values())+[0.0])
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else:
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# print("No data available for this architecture:", mnemonic, file=sys.stderr)
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continue
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for m, p in build_variants(mnemonic, parameters):
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model_data.append((m.lower() + '-' + '_'.join(p),
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throughput, latency, port_occupancy))
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return model_data
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def all_or_false(iterator):
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if not iterator:
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return False
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else:
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return all(iterator)
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def build_variants(mnemonic, parameters):
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"""Yield all resonable variants of this instruction form."""
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# The one that was given
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mnemonic = mnemonic.upper()
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yield mnemonic, parameters
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# Without opmask
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if any(['{opmask}' in p for p in parameters]):
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yield mnemonic, list([p.replace('{opmask}', '') for p in parameters])
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# With suffix (assuming suffix was not already present)
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suffixes = {'Q': 'r64',
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'L': 'r32',
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'W': 'r16',
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'B': 'r8'}
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for s, reg in suffixes.items():
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if not mnemonic.endswith(s) and all_or_false(
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[p == reg for p in parameters if p not in ['mem', 'imd']]):
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yield mnemonic+s, parameters
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def architectures(tree):
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return set([a.attrib['name'] for a in tree.findall('.//architecture')])
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def int_or_zero(s):
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try:
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return int(s)
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except ValueError:
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return 0
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def dump_csv(model_data, arch):
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csv = 'instr,TP,LT,ports\n'
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ports = set()
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for mnemonic, throughput, latency, port_occupancy in model_data:
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for p in port_occupancy:
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ports.add(p)
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ports = sorted(ports)
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# If not all ports have been used (happens with port7 due to blacklist
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# port_occupancy_from_tag_attributes), extend list accordingly:
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while len(ports) < Scheduler.arch_dict[arch] + len(Scheduler.arch_pipeline_ports.get(arch, [])):
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max_index = ports.index(str(max(map(int_or_zero, ports))))
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ports.insert(max_index + 1, str(max(map(int_or_zero, ports)) + 1))
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for mnemonic, throughput, latency, port_occupancy in model_data:
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for p in ports:
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if p not in port_occupancy:
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port_occupancy[p] = 0.0
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po_items = sorted(port_occupancy.items())
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csv_line = '{},{},{},"({})"\n'.format(mnemonic, throughput, latency,
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','.join([str(c) for p, c in po_items]))
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csv += csv_line
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return csv
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('xml', help='path of instructions.xml from http://uops.info')
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parser.add_argument('arch', nargs='?',
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help='architecture to extract, use IACA abbreviations (e.g., SNB). '
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'if not given, all will be extracted and saved to file in CWD.')
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args = parser.parse_args()
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tree = ET.parse(args.xml)
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if args.arch:
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model_data = extract_model(tree, args.arch)
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print(dump_csv(model_data, args.arch))
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else:
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for arch in architectures(tree):
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model_data = extract_model(tree, arch)
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with open('{}_data.csv'.format(arch), 'w') as f:
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f.write(dump_csv(model_data, arch))
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if __name__ == '__main__':
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main()
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File diff suppressed because it is too large
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Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,122 +0,0 @@
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instr,TP,LT,ports
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jae-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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ja-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jbe-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jb-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jc-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jcxz-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jecxz-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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je-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jge-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jg-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jle-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jl-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jmp-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jmpq-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnae-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jna-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnbe-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnb-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnc-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jne-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnge-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jng-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnle-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnl-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jno-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jno-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnp-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jns-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jns-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jnz-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jo-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jo-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jpe-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jp-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jpo-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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js-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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js-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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jz-lbl,0.0,0.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
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add-r32_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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add-r64_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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addl-r32_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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addq-r64_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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addl-mem_imd,1.0,7.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 1.0, 1.0)"
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addq-mem_imd,1.0,7.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 1.0, 1.0)"
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add-mem_r32,1.0,7.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 1.0, 1.0)"
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add-mem_r64,1.0,7.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 1.0, 1.0)"
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addl-mem_r32,1.0,7.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 1.0, 1.0)"
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addq-mem_r64,1.0,7.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 1.0, 1.0)"
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cmp-mem_r32,0.5,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0.5, 0.5)"
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cmpl-mem_r32,0.5,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0.5, 0.5)"
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cmp-r32_mem,0.5,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0.5, 0.5)"
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cmpl-r32_mem,0.5,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0.5, 0.5)"
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cmp-r32_r32,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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cmpl-r32_r32,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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cmp-r64_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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cmp-r64_r64,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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cmpq-r64_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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cmpq-r64_r64,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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inc-r64,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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incq-r64,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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incl-r32,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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mov-mem_r64,1.0,4.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 1.0, 1.0)"
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mov-r64_mem,0.5,3.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
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mov-r32_mem,0.5,3.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
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movq-mem_r64,1.0,4.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 1.0, 1.0)"
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movq-r64_mem,0.5,3.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
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movl-r32_mem,0.5,3.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
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movslq-r64_r32,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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sub-r32_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
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vaddpd-ymm_ymm_mem,1.0,3.0,"(0, 0, 1.0, 1.0, 0, 0, 0, 0, 0, 0.5, 0.5)"
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vaddsd-xmm_xmm_mem,0.5,3.0,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0.5, 0.5)"
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vaddsd-xmm_xmm_xmm,0.5,3.0,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vaddss-xmm_xmm_xmm,0.5,3.0,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vcvtsi2ss-xmm_xmm_r32,1.0,4.0,"(1.0, 1.0, 1.0, 1.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vcvtss2si-r32_xmm,1.0,7.0,"(1.0, 1.0, 1.0, 1.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
cvtsi2ss-xmm_r32,1.0,8.0,"(1.0, 1.0, 1.0, 1.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd213pd-ymm_ymm_ymm,1.0,5.0,"(1.0, 1.0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd213pd-xmm_xmm_xmm,0.5,5.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd213ps-ymm_ymm_ymm,1.0,5.0,"(1.0, 1.0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd213ps-xmm_xmm_xmm,0.5,5.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd213sd-xmm_xmm_xmm,0.5,5.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd213ss-xmm_xmm_xmm,0.5,5.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd132sd-xmm_xmm_mem,0.5,5.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
vfmadd132pd-xmm_xmm_mem,0.5,5.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
vfmadd132pd-ymm_ymm_mem,1.0,5.0,"(1.0, 1.0, 0, 0, 0, 0, 0, 0, 0, 1.0, 1.0)"
|
||||
vinsertf128-ymm_ymm_imd,0.6666666666666667,1.0,"(-1,)"
|
||||
vmovsd-mem_xmm,1.0,8.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 1.0, 1.0)"
|
||||
vmovsd-xmm_mem,0.5,-1.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
vmulpd-ymm_ymm_ymm,1.0,4.0,"(1.0, 1.0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vmulsd-xmm_xmm_mem,0.5,4.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
vmulsd-xmm_xmm_xmm,0.5,4.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vmulss-xmm_xmm_xmm,0.5,3.0,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vsubpd-ymm_ymm_mem,1.0,3.0,"(0, 0, 1.0, 1.0, 0, 0, 0, 0, 0, 1.0, 1.0)"
|
||||
vsubsd-xmm_xmm_mem,0.5,3.0,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
vsubsd-xmm_xmm_xmm,0.5,3.0,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vsubss-xmm_xmm_xmm,0.5,3.0,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vmovaps-xmm_mem,0.5,3.0,"(0.25, 0.25, 0.25, 0.25, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
vmovaps-mem_xmm,1.0,5.0,"(0.25, 0.25, 0.25, 0.25, 0, 0, 0, 0, 0, 1.0, 1.0)"
|
||||
vmovapd-ymm_mem,1.0,-1.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 1.0, 1.0)"
|
||||
vmovapd-mem_ymm,2.0,-1.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 2.0, 2.0)"
|
||||
movq-r64_xmm,1.0,-1.0,"(0, 0, 1.0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
#prefetcht0-mem,0.5,-1.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
#prefetchw-mem,0.5,-1.0,"(0, 0, 0, 0, 0, 0, 0, 0, 0, 0.5, 0.5)"
|
||||
cmpl-r32_imd,0.25,1.0,"(0, 0, 0, 0, 0, 0.25, 0.25, 0.25, 0.25, 0, 0)"
|
||||
vaddpd-xmm_xmm_xmm,0.5,3,"(0, 0, 0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vaddpd-ymm_ymm_ymm,1,3,"(0, 0, 1.0, 1.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vcvtdq2pd-xmm_xmm,1,7,"(0.5, 0.5, 0, 1.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vcvtdq2pd-ymm_xmm,2,7,"(1.0, 1.0, 0, 2.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vcvtsi2sd-xmm_xmm_r32,1,4,"(0, 0, 1.0, 1.0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vextracti128-xmm_ymm_imd,0.3333333333333333,1,"(0.33, 0.33, 0, 0.33, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd132pd-xmm_xmm_xmm,0.5,5,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd132pd-ymm_ymm_ymm,1,5,"(1.0, 1.0, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vfmadd132sd-xmm_xmm_xmm,0.5,5,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vmulpd-xmm_xmm_xmm,0.5,4,"(0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vpaddd-xmm_xmm_xmm,0.3333333333333333,1,"(0.33, 0.33, 0, 0.33, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vpaddd-ymm_ymm_ymm,0.6666666666666667,1,"(0.66, 0.66, 0, 0.66, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vpshufd-xmm_xmm_imd,0.5,1,"(0, 0.5, 0.5, 0, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vxorpd-xmm_xmm_xmm,0.25,1,"(0.25, 0.25, 0.25, 0.25, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vxorps-xmm_xmm_xmm,0.25,1,"(0.25, 0.25, 0.25, 0.25, 0, 0, 0, 0, 0, 0, 0)"
|
||||
vdivpd-xmm_xmm_xmm,4,8,"(0, 0, 0, 1.0, 4.0, 0, 0, 0, 0, 0, 0)"
|
||||
vdivsd-xmm_xmm_xmm,4,8,"(0, 0, 0, 1.0, 4.0, 0, 0, 0, 0, 0, 0)"
|
||||
|
Reference in New Issue
Block a user