added M1 arch

README.rst

@@ -101,7 +101,7 @@ The usage of OSACA can be listed as:
 --arch ARCH
   needs to be replaced with the target architecture abbreviation.
   Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures.
-  Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110,  and ``A64FX`` for Fujitsu's HPC ARM architecture are available.
+  Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, and ``M1`` for the Apple M1-Firestorm performance core are available.
   If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64.
 --fixed
   Run the throughput analysis with fixed port utilization for all suitable ports per instruction.

osaca/osaca.py

@@ -38,6 +38,7 @@ SUPPORTED_ARCHS = [
     "A64FX",
     "TSV110",
     "A72",
+    "M1",
 ]
 DEFAULT_ARCHS = {
     "aarch64": "A64FX",
@@ -101,7 +102,7 @@ def create_parser(parser=None):
         "--arch",
         type=str,
         help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, "
-        "A64FX, TSV110, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
+        "A64FX, TSV110, A72, M1). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
     )
     parser.add_argument(
         "--fixed",

osaca/semantics/hw_model.py

@@ -281,6 +281,7 @@ class MachineModel(object):
             "a72": "aarch64",
             "tx2": "aarch64",
             "n1": "aarch64",
+            "m1": "aarch64",
             "zen1": "x86",
             "zen+": "x86",
             "zen2": "x86",