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more instructions
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@@ -161,6 +161,13 @@ instruction_forms:
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throughput: 0.5
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latency: 6.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0]
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- latency: ~
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name: "fmov"
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operands:
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- {class: "register", prefix: "s"}
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- {class: "immediate", imd: "double"}
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port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0]
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throughput: 0.5
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- name: "fmul"
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operands:
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- class: "register"
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@@ -366,6 +373,22 @@ instruction_forms:
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throughput: 0.5
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latency: 5.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0]
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- name: "prfm"
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operands:
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- class: "prfop"
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type: "pld"
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target: "l1"
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policy: "keep"
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- class: "memory"
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base: "x"
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offset: "imd"
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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throughput: ~
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latency: ~
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port_pressure: ~
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- name: "stp"
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operands:
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- class: "register"
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@@ -1,3 +1,5 @@
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// mov x1, #111
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// .byte 213,3,32,31
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.LBB0_32:
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ldp q4, q5, [x9, #-32]
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ldp q6, q7, [x9], #64
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@@ -20,5 +22,6 @@
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fmov s0, -1.0e+0
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fmov s1, #2.0f
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prfm pldl1keep, [x26, #2112]
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b.ne .LBB0_32
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// mov x1, #222
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// .byte 213,3,32,31
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@@ -131,24 +131,24 @@ class TestSemanticTools(unittest.TestCase):
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def test_kernelDG_AArch64(self):
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dg = KernelDG(self.kernel_AArch64, self.parser_AArch64, self.machine_model_tx2)
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self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=2)), {6, 7})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=3)), {8, 9})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=4)), {5, 6, 7})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=5)), {8, 9})
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=6)), 12)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=7)), 13)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=8)), 15)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=9)), 16)
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=10)), {12, 13})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=11)), {15, 16})
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=12)), 14)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=13)), 14)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=14))), 0)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=15)), 17)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=16)), 17)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=17))), 0)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=18))), 0)
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=4)), {8, 9})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=5)), {10, 11})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=6)), {7, 8, 9})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=7)), {10, 11})
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=8)), 14)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=9)), 15)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=10)), 17)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=11)), 18)
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=12)), {14, 15})
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self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=13)), {17, 18})
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=14)), 16)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=15)), 16)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=16))), 0)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=17)), 19)
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self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=18)), 19)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=19))), 0)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=20))), 0)
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self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=21))), 0)
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def test_is_read_is_written_x86(self):
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# independent form HW model
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