3 Commits

Author	SHA1	Message	Date
Metehan Dundar	074118dee0	RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests ... - Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples	2025-06-30 00:28:52 +02:00
Metehan Dundar	aae31fb69b	Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files	2025-05-08 11:57:06 +02:00
Metehan Dundar	b0a5e8cfe9	Parser for RISCV is implemented and tested with a ... simple kernel. Changes to be committed: modified: osaca/parser/__init__.py new file: osaca/parser/parser_RISCV.py new file: tests/test_files/kernel_riscv.s new file: tests/test_parser_RISCV.py	2025-03-04 00:44:38 +01:00