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  • bc91ab3b70 Merge branch 'master' of github.com:RRZE-HPC/OSACA master JanLJL 2026-01-23 12:42:27 +01:00
  • 1d5c1ed9fb Add second semantics.assign_optimal_throughput() call Jan 2026-01-23 12:40:45 +01:00
  • ae54403370 Merge pull request #120 from stefandesouza/master Jan 2026-01-23 12:37:52 +01:00
  • aab76d0c6c fixed bug in DFS for instruction forms with multiple port_pressure assignments + test JanLJL 2026-01-22 17:56:16 +01:00
  • f3b42b6efb consider GAS suffixes when combining LD/ST throughput JanLJL 2026-01-22 17:52:04 +01:00
  • ec32ba5e17 add syntax property for parsers and fix bug for VEX/non-VEX replacement JanLJL 2026-01-22 17:26:03 +01:00
  • 1c058435bb fixed wrong port assignment JanLJL 2026-01-22 17:14:01 +01:00
  • 1de96672fd fixed wrong port assignment and accounted for 1cy div penalty JanLJL 2026-01-22 17:13:28 +01:00
  • e0d6273e59 Add tests for negative offset directly after identifier and after a space as well souza 2026-01-20 09:58:54 +01:00
  • e739bcb1d4 Update parser to allow both postive and negative displacements souza 2026-01-20 09:58:37 +01:00
  • 385194cb15 Fix the string literal check to the dict key souza 2026-01-19 16:58:28 +01:00
  • 504054384c Remove duplicated call souza 2026-01-19 16:38:45 +01:00
  • 60d725bd93 fixed wrong imd keys JanLJL 2026-01-14 11:09:09 +01:00
  • be6a063121 fixed imprecise operand comparison JanLJL 2026-01-14 11:08:53 +01:00
  • a9a8a49d1a formatting JanLJL 2026-01-13 11:14:47 +01:00
  • edd15a2fb7 more instructions from ibench JanLJL 2026-01-13 11:12:37 +01:00
  • f3ecee28d1 initial support for Zen5 JanLJL 2026-01-12 19:47:00 +01:00
  • 6f9b7c4e89 recovered original step order JanLJL 2025-12-22 12:44:26 +01:00
  • 162215d912 added codecov slug JanLJL 2025-12-22 12:41:39 +01:00
  • c0c39d5f85 added codecov token JanLJL 2025-12-22 12:04:22 +01:00
  • 67f889a719 upgraded codecov to v5 JanLJL 2025-12-22 11:28:52 +01:00
  • 383912162b formatting JanLJL 2025-12-22 11:28:35 +01:00
  • 5550b1a720 fixed vextractf64x2 value JanLJL 2025-12-18 17:31:37 +01:00
  • 2460c8e531 improved x86 AT&T parser JanLJL 2025-12-18 17:26:49 +01:00
  • 522e969f7d removed duplicate instruction forms JanLJL 2025-12-09 12:32:37 +01:00
  • bded3bd893 fixed typo JanLJL 2025-12-03 21:10:40 +01:00
  • 6abea6249a version bump v0.7.1 JanLJL 2025-09-08 16:36:20 +02:00
  • 187473b72c fixed bugs in x86intel parser (ZMM and masking support) JanLJL 2025-09-08 16:35:36 +02:00
  • 45847e69ff formatting for black JanLJL 2025-08-16 14:13:29 +02:00
  • 94cb3de6a1 fix bug to support 0x.. and ..R hex values for intel syntax JanLJL 2025-08-16 14:08:43 +02:00
  • 63cb61b423 add pseudo-ops for vcmpps/vcmppd JanLJL 2025-08-14 13:34:45 +02:00
  • b68ce9afc1 new instructions JanLJL 2025-08-13 14:43:17 +02:00
  • c274a25e1b updated retired uops per cy JanLJL 2025-08-13 14:42:45 +02:00
  • 714319e613 new instructions JanLJL 2025-08-13 14:42:30 +02:00
  • 590f915f85 add fallback check w/ and w/o VEX prefix to AT&T to match intel syntax JanLJL 2025-08-13 14:39:15 +02:00
  • b4978c724a Merge pull request #117 from pleroy/Load2 Jan 2025-08-12 16:14:34 +02:00
  • 88d3f1a7a0 Fix a Flake8 diagnostic. pleroy 2025-07-29 18:55:51 +02:00
  • a8fca2afdb Format code with black and fix flake8 linting issues dev/risc-v Metehan Dundar 2025-07-11 22:28:29 +02:00
  • ebf76caa18 Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames Metehan Dundar 2025-07-11 18:15:51 +02:00
  • 61b52dbf28 RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests Metehan Dundar 2025-06-30 00:28:52 +02:00
  • 480c0dcac0 Merge branch 'master' into dev/risc-v Metehan Dundar 2025-05-08 12:23:22 +02:00
  • aa3753d024 Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files Metehan Dundar 2025-05-08 11:57:06 +02:00
  • 5635d2d8df Skip non-integer line numbers in frontend pleroy 2025-03-31 22:44:57 +02:00
  • faa63ce95e Support non-integer line numbers in frontend pleroy 2025-03-31 22:35:09 +02:00
  • 4578eb00fa Flake8 pleroy 2025-03-31 21:37:11 +02:00
  • 3456f6e24a After egg’s review. pleroy 2025-01-05 14:14:05 +01:00
  • df0351d087 Readying. pleroy 2025-01-05 12:13:50 +01:00
  • 969500d79f Merge test pleroy 2025-01-05 00:50:57 +01:00
  • 685ed1e1e1 Graphing. pleroy 2025-01-04 19:17:48 +01:00
  • af9c10f308 Cleanup. pleroy 2025-01-04 19:01:11 +01:00
  • 4255c11010 The tests are passing. pleroy 2025-01-04 18:59:38 +01:00
  • 56fbe1d172 Some more stuff. pleroy 2025-01-04 18:28:57 +01:00
  • aeda9b1d33 Merge imports pleroy 2025-01-04 15:55:33 +01:00
  • 2c4a545f3b Merge pull request #116 from eggrobin/graph-colouring Jan 2025-03-31 11:38:23 +02:00
  • 33fd0a0352 Merge pull request #116 from eggrobin/graph-colouring Jan 2025-03-31 11:38:23 +02:00
  • 25bcf59789 Merge pull request #115 from pleroy/Comisd Jan 2025-03-31 11:18:09 +02:00
  • a17e79a3a9 Merge pull request #115 from pleroy/Comisd Jan 2025-03-31 11:18:09 +02:00
  • da2ce51446 white on blue Robin Leroy 2025-01-02 03:06:14 +01:00
  • de0b1fde64 white on blue Robin Leroy 2025-01-02 03:06:14 +01:00
  • 4526baa6ae Less clever and more useful colouring Robin Leroy 2025-01-01 23:13:52 +01:00
  • d82bc8052b Less clever and more useful colouring Robin Leroy 2025-01-01 23:13:52 +01:00
  • 9040757e91 Improve dependency graph colouring Robin Leroy 2025-01-01 18:34:28 +01:00
  • b854562a82 Improve dependency graph colouring Robin Leroy 2025-01-01 18:34:28 +01:00
  • 638d938325 Mark backward edges as backward so the graph is ordered like the code Robin Leroy 2025-01-01 04:03:09 +01:00
  • 8c31c6ff77 Mark backward edges as backward so the graph is ordered like the code Robin Leroy 2025-01-01 04:03:09 +01:00
  • a4c6d84b0c Don’t spam filled until dot breaks Robin Leroy 2025-01-01 03:55:51 +01:00
  • e096cf4704 Don’t spam filled until dot breaks Robin Leroy 2025-01-01 03:55:51 +01:00
  • 034d192c57 Don’t run out of colours Robin Leroy 2024-12-30 21:48:15 +01:00
  • 7d900fde38 Don’t run out of colours Robin Leroy 2024-12-30 21:48:15 +01:00
  • ed263f696a Moar colors. pleroy 2024-12-30 19:14:17 +01:00
  • 28df996617 Moar colors. pleroy 2024-12-30 19:14:17 +01:00
  • 939089030b Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write. pleroy 2024-12-29 18:11:15 +01:00
  • 1eb82a6f0a Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write. pleroy 2024-12-29 18:11:15 +01:00
  • d2b8b7771f ucomisd is like comisd Robin Leroy 2024-12-30 22:50:03 +01:00
  • b7e4acc905 ucomisd is like comisd Robin Leroy 2024-12-30 22:50:03 +01:00
  • ea59056f94 Define comisd sources. pleroy 2024-12-30 19:55:20 +01:00
  • b989145a36 Define comisd sources. pleroy 2024-12-30 19:55:20 +01:00
  • ce0f78e441 Merge pull request #114 from eggrobin/setmeow-jmeow Jan 2025-03-26 09:05:23 +01:00
  • 9c97d32512 Merge pull request #114 from eggrobin/setmeow-jmeow Jan 2025-03-26 09:05:23 +01:00
  • d782f06e84 Add RISC-V support and update version to 0.6.2 Metehan Dundar 2025-03-21 17:16:39 +01:00
  • 122f8a674b Configure the dependencies of the jmeow instructions on flags Robin Leroy 2025-01-05 18:21:44 +01:00
  • 9e6373a013 Configure the dependencies of the jmeow instructions on flags Robin Leroy 2025-01-05 18:21:44 +01:00
  • 94f32c51a7 Add the setmeow instructions Robin Leroy 2025-01-01 06:07:01 +01:00
  • e99c3d935d Add the setmeow instructions Robin Leroy 2025-01-01 06:07:01 +01:00
  • 734979521b use pypi version of kerncraft for GH Actions JanLJL 2025-03-19 14:36:49 +01:00
  • edb32b38ca use pypi version of kerncraft for GH Actions JanLJL 2025-03-19 14:36:49 +01:00
  • 1627f0e49d version bump JanLJL 2025-03-17 10:28:06 +01:00
  • 2a231bf20b version bump v0.7.0 JanLJL 2025-03-17 10:28:06 +01:00
  • 68252c86b9 remove AT&T limitation JanLJL 2025-03-17 10:27:41 +01:00
  • fb8c8ec7db remove AT&T limitation JanLJL 2025-03-17 10:27:41 +01:00
  • d4d84fa49e add syntax flag in README Jan 2025-03-17 10:26:50 +01:00
  • 2f069000e9 add syntax flag in README Jan 2025-03-17 10:26:50 +01:00
  • 2b838b7bdd Merge pull request #112 from pleroy/Intel Jan 2025-03-17 10:20:40 +01:00
  • bdbcb18817 Merge pull request #112 from pleroy/Intel Jan 2025-03-17 10:20:40 +01:00
  • 31f5912af6 take +- operator of offset/index in mem-addr into account JanLJL 2025-03-14 15:40:16 +01:00
  • 7930e4d704 take +- operator of offset/index in mem-addr into account JanLJL 2025-03-14 15:40:16 +01:00
  • 850f7edc6b RISCV.yml file has been updated. Metehan Dundar 2025-03-13 09:54:06 +01:00
  • 732dd95810 Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. pleroy 2025-03-12 22:26:38 +01:00
  • d61330404b Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. pleroy 2025-03-12 22:26:38 +01:00
  • f846f0ed7d Upper case the argument to the --syntax flag, otherwise 'att' means 'intel' :-/ pleroy 2025-03-12 00:29:10 +01:00