mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-13 07:30:06 +01:00
take +- operator of offset/index in mem-addr into account
This commit is contained in:
JanLJL
pleroy
@@ -321,9 +321,7 @@ class ParserX86Intel(ParserX86):
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base = base_register.setResultsName("base")
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displacement = pp.Group(
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pp.Group(
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integer_number ^ identifier
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).setResultsName(self.immediate_id)
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pp.Group(integer_number ^ identifier).setResultsName(self.immediate_id)
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).setResultsName("displacement")
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short_indexed = index_register.setResultsName("index")
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long_indexed = (
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@@ -331,11 +329,10 @@ class ParserX86Intel(ParserX86):
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+ pp.Literal("*")
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+ scale.setResultsName("scale")
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)
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indexed = pp.Group(
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short_indexed
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^ long_indexed
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).setResultsName("indexed")
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indexed = pp.Group(short_indexed ^ long_indexed).setResultsName("indexed")
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operator = pp.Word("+-", exact=1)
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operator_index = pp.Word("+-", exact=1).setResultsName("operator_idx")
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operator_displacement = pp.Word("+-", exact=1).setResultsName("operator_disp")
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# Syntax:
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# `base` always preceedes `indexed`.
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@@ -347,16 +344,24 @@ class ParserX86Intel(ParserX86):
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pp.Literal("[")
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+ (
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base
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^ (base + operator + displacement)
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^ (base + operator + displacement + operator + indexed)
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^ (base + operator + indexed)
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^ (base + operator + indexed + operator + displacement)
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^ (base + operator_displacement + displacement)
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^ (base + operator_displacement + displacement + operator_index + indexed)
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^ (base + operator_index + indexed)
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^ (base + operator_index + indexed + operator_displacement + displacement)
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^ (displacement + operator + base)
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^ (displacement + operator + base + operator + indexed)
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^ (displacement + operator + pp.Group(long_indexed).setResultsName("indexed"))
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^ (displacement + operator + base + operator_index + indexed)
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^ (
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displacement
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+ operator_index
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+ pp.Group(long_indexed).setResultsName("indexed")
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)
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^ pp.Group(long_indexed).setResultsName("indexed")
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^ (pp.Group(long_indexed).setResultsName("indexed") + operator + displacement)
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)
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^ (
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pp.Group(long_indexed).setResultsName("indexed")
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+ operator_displacement
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+ displacement
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)
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)
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+ pp.Literal("]")
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).setResultsName("register_expression")
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@@ -373,7 +378,7 @@ class ParserX86Intel(ParserX86):
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self.register.setResultsName("segment") + pp.Literal(":") + immediate
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^ immediate + register_expression
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^ register_expression
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^ identifier + pp.Optional(pp.Literal("+") + immediate)
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^ identifier + pp.Optional(operator + immediate)
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).setResultsName("address_expression")
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offset_expression = pp.Group(
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@@ -665,9 +670,11 @@ class ParserX86Intel(ParserX86):
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if indexed:
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index = indexed.get("index")
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scale = int(indexed.get("scale", "1"), 0)
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displacement_op = (
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self.process_immediate(displacement.immediate) if displacement else None
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)
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if register_expression.get("operator_index") == "-":
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scale *= -1
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displacement_op = self.process_immediate(displacement.immediate) if displacement else None
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if displacement_op and register_expression.get("operator_disp") == "-":
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displacement_op.value *= -1
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base_op = RegisterOperand(name=base.name) if base else None
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index_op = RegisterOperand(name=index.name) if index else None
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new_memory = MemoryOperand(
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@@ -724,6 +731,8 @@ class ParserX86Intel(ParserX86):
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if "displacement" in offset_expression
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else None
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)
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if displacement and "operator_disp" == "-":
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displacement.value *= -1
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identifier = self.process_identifier(offset_expression.identifier)
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identifier.offset = displacement
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return MemoryOperand(offset=identifier)
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@@ -1,15 +1,15 @@
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; Translated from kernel_x86_memdep.s
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L4:
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vmovsd [rax+8], xmm0
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add rax, 8
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vmovsd [rax+rcx*8+8], xmm0
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vaddsd xmm0, xmm0, [rax]
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sub rax, -8
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vaddsd xmm0, xmm0, [rax-8]
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dec rcx
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vaddsd xmm0, xmm0, [rax+rcx*8+8]
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mov rdx, rcx
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vaddsd xmm0, xmm0, [rax+rdx*8+8]
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vmovsd [rax+8], xmm0 # line 3 <---------------------------------+
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add rax, 8 # rax=rax_orig+8 |
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vmovsd [rax+rcx*8+8], xmm0 # line 5 <------------------------------------------+
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vaddsd xmm0, xmm0, [rax] # depends on line 3, rax+8;[rax] == [rax+8] --------+ |
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sub rax, -8 # rax=rax_orig+16 | |
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vaddsd xmm0, xmm0, [rax-8] # depends on line 3, rax+16;[rax-8] == [rax+8] -----+ |
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dec rcx # rcx=rcx_orig-1 |
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vaddsd xmm0, xmm0, [rax+rcx*8+8] # depends on line 5, [(rax+8)+(rcx-1)*8+8] == [rax+rcx*+8] --+
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mov rdx, rcx # |
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vaddsd xmm0, xmm0, [rax+rdx*8+8] # depends on line 5, rcx == rdx -----------------------------+
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vmulsd xmm0, xmm0, xmm1
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add rax, 8
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cmp rsi, rax
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@@ -209,15 +209,17 @@ class TestParserX86Intel(unittest.TestCase):
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self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator"))
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self.assertEqual(parsed_14.mnemonic, "vaddsd")
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self.assertEqual(parsed_14.operands[0],
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RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_14.operands[1],
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RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_14.operands[2],
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MemoryOperand(base=RegisterOperand(name="RDX"),
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offset=ImmediateOperand(value=8),
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index=RegisterOperand(name="RAX"),
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scale=8))
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self.assertEqual(parsed_14.operands[0], RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_14.operands[1], RegisterOperand(name="XMM0"))
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self.assertEqual(
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parsed_14.operands[2],
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MemoryOperand(
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base=RegisterOperand(name="RDX"),
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offset=ImmediateOperand(value=8),
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index=RegisterOperand(name="RAX"),
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scale=8,
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),
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)
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def test_parse_line(self):
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line_comment = "; -- Begin main"
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@@ -363,21 +365,32 @@ class TestParserX86Intel(unittest.TestCase):
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parsed = self.parser.parse_file(self.gs_gcc_code)
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self.assertEqual(parsed[0].line_number, 1)
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# Check a few lines to make sure that we produced something reasonable.
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self.assertEqual(parsed[61],
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InstructionForm(mnemonic="vaddsd",
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operands=[RegisterOperand("XMM0"),
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RegisterOperand("XMM0"),
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MemoryOperand(base=RegisterOperand("RDX"),
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index=RegisterOperand("RAX"),
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scale=8,
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offset=ImmediateOperand(value=8))],
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line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]",
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line_number=62))
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self.assertEqual(parsed[101],
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InstructionForm(directive_id=DirectiveOperand(name=".long",
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parameters=["1072939201"]),
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line=" .long 1072939201",
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line_number=102))
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self.assertEqual(
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parsed[61],
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InstructionForm(
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mnemonic="vaddsd",
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operands=[
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RegisterOperand("XMM0"),
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RegisterOperand("XMM0"),
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MemoryOperand(
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base=RegisterOperand("RDX"),
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index=RegisterOperand("RAX"),
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scale=8,
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offset=ImmediateOperand(value=8),
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),
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],
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line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]",
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line_number=62,
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),
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)
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self.assertEqual(
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parsed[101],
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InstructionForm(
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directive_id=DirectiveOperand(name=".long", parameters=["1072939201"]),
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line=" .long 1072939201",
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line_number=102,
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),
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)
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self.assertEqual(len(parsed), 102)
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def test_normalize_imd(self):
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