10 Commits

Author	SHA1	Message	Date
Metehan Dundar	074118dee0	RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests ... - Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples	2025-06-30 00:28:52 +02:00
JanLJL	5cd6b2cf9d	renamed .asm files to .s for consistency	2025-03-05 09:36:07 +01:00
pleroy	1a7c1588f6	Add support for the Intel syntax supported by MSVC and ICC	2025-02-02 14:02:16 +01:00
stefandesouza	38781ecc94	Port pressure returned in tuple with Memory Operand	2024-03-04 20:00:43 +01:00
stefandesouza	cac4a0ebf2	flake8 standards	2023-12-03 21:04:58 +01:00
stefandesouza	0a32c77751	Added 2 operand types and made changes for attribute usage	2023-08-20 21:01:44 +02:00
Julian Hammer	6204c90934	migrate code style to Black	2021-03-11 12:02:45 +01:00
JanLJL	022598d94f	autodetect ISA and default uarch for ISA	2020-10-29 13:00:02 +01:00
JanLJL	04db2bfa79	added tests for asmbench import	2020-02-20 12:07:20 +01:00
JanLJL	eeb55e8cf7	added tests for base parser	2019-08-30 12:10:15 +02:00