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074118dee0820a4f56b7d38c62002c637f457c73
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4 Commits

Author SHA1 Message Date
Metehan Dundar
074118dee0 RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests 
- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
 2025-06-30 00:28:52 +02:00
Metehan Dundar
83ca46bcc4 Add RISC-V support and update version to 0.6.2 2025-03-21 17:16:39 +01:00
Metehan Dundar
685c9f3225 Add initial support for RISC-V architecture and update relevant files 2025-03-11 05:10:03 +01:00
Metehan Dundar
b0a5e8cfe9 Parser for RISCV is implemented and tested with a 
simple kernel.

Changes to be committed:
	modified:   osaca/parser/__init__.py
	new file:   osaca/parser/parser_RISCV.py
	new file:   tests/test_files/kernel_riscv.s
	new file:   tests/test_parser_RISCV.py
 2025-03-04 00:44:38 +01:00