Metehan Dundar
1ceac6e9f3
Refactor: RISC-V parser, code formatting, and flake8 compliance
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- Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand.
- Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility.
- Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase.
- Improved docstrings and split long lines for better readability.
- Fixed test failures related to ImmediateOperand instantiation and attribute errors.
- Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64.
- Updated .gitignore and documentation as needed.
- Renamed example files for consistency (rv6 -> rv64).
2025-07-04 23:21:06 +02:00
JanLJL
ffb5f0eb55
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
bcecabd911
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
63f56e50b4
black formatting
2025-03-05 10:20:47 +01:00
pleroy
b4d342266d
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
aeecac3b5f
Black formatting
2024-05-02 17:04:56 +02:00
stefandesouza
9cd841cd08
Added updated files
2024-02-27 14:47:55 +01:00
stefandesouza
33ad20dc3a
More formatting
2024-01-10 13:26:50 +01:00
stefandesouza
405a1d2857
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
47a44c9865
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
1885ce6ddb
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
e77dfb4eb3
Fixed issue with throughput assignment
2023-10-30 19:32:05 +01:00
stefandesouza
78ca6fe855
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
cce05e44cb
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
17cd1a70c7
Updated tests to use the now class style iforms in isa_data
2023-10-23 16:25:31 +02:00
stefandesouza
fad1997b76
Included 'source' and 'destination' attributes when loading isa data
2023-10-16 15:48:47 +02:00
stefandesouza
bc058233a3
Changing operand matching for class operand style
2023-09-25 21:35:17 +02:00
stefandesouza
2f8c2f56cf
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
a761ee43f1
Converting operand types read in from YAML files
2023-09-12 00:23:59 +02:00
stefandesouza
14ecefd677
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
0f182551f2
Changes to accomodate the new OO style
2023-08-28 15:19:46 +02:00
stefandesouza
5ca37a2a3f
Added 2 operand types and made changes for attribute usage
2023-08-20 21:01:44 +02:00
stefan.desouza@outlook.com
b70916e4f8
Classes for OperandForm and Operand types
2023-08-07 15:01:48 +02:00
JanLJL
97756faa04
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
0985e81b23
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
2cc338d107
formatting according to black
2023-03-03 15:24:18 +01:00
JanLJL
72f69fa707
added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes
2023-03-03 15:11:40 +01:00
JanLJL
54da7568d9
small bugfixes
2022-03-17 16:38:28 +01:00
JanLJL
bc7761007c
fixed formatting with correct line length
2021-10-04 15:00:17 +02:00
JanLJL
217fcff664
black conformity
2021-09-30 15:53:56 +02:00
JanLJL
3404d72dc5
enhanced parser
2021-09-29 17:26:27 +02:00
JanLJL
1b40c10a1f
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
5038ce7a15
changed immediate type from str to int
2021-05-10 01:12:30 +02:00
Julian Hammer
781b8b6b89
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
04836cf3f9
Validation ( #71 )
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Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
afa607e546
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
e29cfb3185
new caching structure with support for distribution
2020-10-28 16:29:55 +01:00
Julian
e159fc938f
Merge pull request #51 from RRZE-HPC/A64FX
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A64FX support and several Arm bugfixes and enhancements including better TP scheduling
2020-10-16 10:44:47 +02:00
Julian Hammer
f0c84c3aee
treating post- and pre-incremeted memory references no longer as src_dst
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the incremented register is now considered src_dst instead
2020-10-13 19:25:29 +02:00
JanLJL
7bc39c1343
prepared for aarch64 8.2 support
2020-07-23 15:54:54 +02:00
JanLJL
68964bb2a1
enhanced TP scheduling
2020-07-06 18:49:46 +02:00
JanLJL
9318181902
added reg-only fallback for mem-instructions not found in ISA DB
2020-03-10 17:15:57 +01:00
JanLJL
52ca93ad03
added documentation
2020-03-09 16:35:06 +01:00
JanLJL
2c2e381278
supports hidden operands now (for flags or special instructions)
2020-01-14 20:54:00 +01:00
JanLJL
dce0b8e753
adjusted for mem wildcards in AArch64 ISA DB
2020-01-10 14:38:17 +01:00
JanLJL
e250f69821
added --ignore-unknown flag and major updates in x86 parser
2020-01-09 17:57:08 +01:00
Julian Hammer
63ca1e66bf
FIX #46 untangled semantic and non-semantic operand info
2019-11-14 16:43:33 +01:00
