Metehan Dundar
1ceac6e9f3
Refactor: RISC-V parser, code formatting, and flake8 compliance
...
- Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand.
- Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility.
- Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase.
- Improved docstrings and split long lines for better readability.
- Fixed test failures related to ImmediateOperand instantiation and attribute errors.
- Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64.
- Updated .gitignore and documentation as needed.
- Renamed example files for consistency (rv6 -> rv64).
2025-07-04 23:21:06 +02:00
Metehan Dundar
61b52dbf28
RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests
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- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
2025-06-30 00:28:52 +02:00
Metehan Dundar
480c0dcac0
Merge branch 'master' into dev/risc-v
2025-05-08 12:23:22 +02:00
pleroy
939089030b
Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.
2025-03-27 22:47:32 +01:00
Metehan Dundar
d782f06e84
Add RISC-V support and update version to 0.6.2
2025-03-21 17:16:39 +01:00
JanLJL
31f5912af6
take +- operator of offset/index in mem-addr into account
2025-03-14 18:46:12 +01:00
pleroy
732dd95810
Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle.
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I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.
2025-03-12 22:26:38 +01:00
Metehan Dundar
a75098c9f5
Add RISCV parser to test suite
2025-03-11 11:42:15 +01:00
Metehan Dundar
653c27135d
Add initial support for RISC-V architecture and update relevant files
2025-03-11 05:10:03 +01:00
JanLJL
ffb5f0eb55
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
bcecabd911
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
b7e5df0a08
more black formatting
2025-03-05 10:40:18 +01:00
JanLJL
fb7f1a289d
flake8 formatting
2025-03-05 10:19:10 +01:00
JanLJL
a4939d1873
renamed .asm files to .s for consistency
2025-03-05 09:36:07 +01:00
JanLJL
4e6d37aa9f
bugfixes
2025-03-04 17:46:37 +01:00
JanLJL
1c2e0f3921
chmod +x
2025-03-04 17:46:23 +01:00
JanLJL
3de6097a06
add test case for specific syntax parameter in get_asm_parser()
2025-03-04 17:45:19 +01:00
Metehan Dundar
7e546d970f
Parser for RISCV is implemented and tested with a
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simple kernel.
Changes to be committed:
modified: osaca/parser/__init__.py
new file: osaca/parser/parser_RISCV.py
new file: tests/test_files/kernel_riscv.s
new file: tests/test_parser_RISCV.py
2025-03-04 00:44:38 +01:00
pleroy
b4d342266d
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
3cf2d02b7a
formatting
2024-08-19 15:52:28 +02:00
Markus Büttner
14414fac01
Update parsing of memory segments
...
This addresses issue discussed in RRZE-HPC/OSACA#107 .
Now it can parse instructions of the form
%fs:var@RELOC
%fs:var@RELOC+4
%fs:var@RELOC(%rdi)
2024-07-30 16:02:16 +02:00
JanLJL
17e9b80282
formattign
2024-05-02 16:30:11 +02:00
JanLJL
2e29f0b4e1
moved get_full_instruction_name() from HardwareModel to DBInterface
2024-05-02 16:25:41 +02:00
stefandesouza
ae2fcfe8bb
added prefetch operand
2024-03-18 22:29:39 +01:00
stefandesouza
e253638cb7
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
fa56fd0183
Uncommented tests
2024-03-05 00:19:29 +01:00
stefandesouza
4ec3788f58
Dump now converts classes to dicts
2024-03-05 00:18:45 +01:00
stefandesouza
62c21a7f31
Port pressure returned in tuple with Memory Operand
2024-03-04 20:00:43 +01:00
stefandesouza
9cd841cd08
Added updated files
2024-02-27 14:47:55 +01:00
stefandesouza
0474148d7b
Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples
2024-02-24 21:03:15 +01:00
stefandesouza
d7768e5a8a
Removed comments from operands
2024-02-24 14:15:25 +01:00
stefandesouza
33ad20dc3a
More formatting
2024-01-10 13:26:50 +01:00
stefandesouza
9a7f38396f
Formatting before PR
2024-01-10 13:05:27 +01:00
stefandesouza
a2c67f1a61
Added shift and shift_op to Register Operand
2024-01-04 14:34:36 +01:00
stefandesouza
f93ce644ec
Merged master
2023-12-16 12:15:12 +01:00
stefandesouza
405a1d2857
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
47a44c9865
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
1885ce6ddb
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
e77dfb4eb3
Fixed issue with throughput assignment
2023-10-30 19:32:05 +01:00
stefandesouza
78ca6fe855
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
cce05e44cb
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
a11d0f1845
Hidden operands and dependency break in iforms now included
2023-10-23 21:54:58 +02:00
stefandesouza
528fa2c959
Updated db_interface files to work with class objects
2023-10-23 18:19:35 +02:00
stefandesouza
17cd1a70c7
Updated tests to use the now class style iforms in isa_data
2023-10-23 16:25:31 +02:00
stefandesouza
d664db316c
frontend tests now use new OO style, removed AttrDict usage
2023-10-22 16:43:46 +02:00
stefandesouza
d81a8df7e7
Convert isa_data iforms to InstructionForm type
2023-10-17 12:28:49 +02:00
stefandesouza
fad1997b76
Included 'source' and 'destination' attributes when loading isa data
2023-10-16 15:48:47 +02:00
