Commit Graph

41 Commits

Author SHA1 Message Date
Metehan Dundar
1ceac6e9f3 Refactor: RISC-V parser, code formatting, and flake8 compliance
- Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand.
- Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility.
- Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase.
- Improved docstrings and split long lines for better readability.
- Fixed test failures related to ImmediateOperand instantiation and attribute errors.
- Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64.
- Updated .gitignore and documentation as needed.
- Renamed example files for consistency (rv6 -> rv64).
2025-07-04 23:21:06 +02:00
JanLJL
bcecabd911 added support for <Xd>! registers and [<Xd>]! mem addresses in Arm 2025-03-07 11:49:14 +01:00
JanLJL
17e9b80282 formattign 2024-05-02 16:30:11 +02:00
stefandesouza
ae2fcfe8bb added prefetch operand 2024-03-18 22:29:39 +01:00
stefandesouza
e253638cb7 Black formatting 2024-03-05 12:14:05 +01:00
stefandesouza
4ec3788f58 Dump now converts classes to dicts 2024-03-05 00:18:45 +01:00
stefandesouza
62c21a7f31 Port pressure returned in tuple with Memory Operand 2024-03-04 20:00:43 +01:00
stefandesouza
9cd841cd08 Added updated files 2024-02-27 14:47:55 +01:00
stefandesouza
d7768e5a8a Removed comments from operands 2024-02-24 14:15:25 +01:00
stefandesouza
9a7f38396f Formatting before PR 2024-01-10 13:05:27 +01:00
stefandesouza
a2c67f1a61 Added shift and shift_op to Register Operand 2024-01-04 14:34:36 +01:00
stefandesouza
47a44c9865 Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes 2023-12-10 17:26:43 +01:00
stefandesouza
1885ce6ddb flake8 standards 2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb Black formatting 2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a Fixed semantic and marker tests. Now only dump needs to be adjusted 2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7 pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also 2023-12-02 16:56:43 +01:00
stefandesouza
78ca6fe855 Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working 2023-10-29 16:36:00 +01:00
stefandesouza
cce05e44cb Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class 2023-10-29 13:52:49 +01:00
stefandesouza
2f8c2f56cf Black formatting 2023-09-12 12:45:28 +02:00
stefandesouza
14ecefd677 Changes for operand matching, instruction loading 2023-09-11 18:23:57 +02:00
stefandesouza
72a17ac8c8 Updated list/range register resolver & applied black formatting 2023-08-26 14:51:04 +02:00
stefandesouza
47b8dba572 Removed all AttrDict() usage in parser. process_operand() now turns single registers into operands 2023-08-21 18:53:56 +02:00
stefandesouza
9d54b4da47 Added eq methods, changed AArch parser tests for class usage 2023-08-21 15:36:40 +02:00
stefandesouza
5ca37a2a3f Added 2 operand types and made changes for attribute usage 2023-08-20 21:01:44 +02:00
stefandesouza
17ef6582d1 InstrucForm class usage in AArch parser 2023-08-20 13:35:11 +02:00
stefandesouza
4a382193a5 Separate operand files with inheritance, str and repr classes 2023-08-20 12:10:07 +02:00
stefandesouza
1d5ff61890 Added seperate operand class files 2023-08-20 11:38:56 +02:00
JanLJL
261039e51e black-compliant formatting 2023-03-14 18:22:27 +01:00
JanLJL
97756faa04 Merge branch 'master' into pr-armcc 2023-03-14 17:50:48 +01:00
JanLJL
0985e81b23 added more dependency analysis for post/pre indexing and condition flags 2023-03-14 17:00:02 +01:00
JanLJL
c1373fe44c enabled indexing without shape and lane for vector regs 2023-03-03 14:41:48 +01:00
JanLJL
1b40c10a1f applied flake8 and black rules 2021-08-26 16:58:19 +02:00
JanLJL
ec771dbe91 fixed parsing of reg ranges and lists 2021-06-01 00:10:05 +02:00
JanLJL
5038ce7a15 changed immediate type from str to int 2021-05-10 01:12:30 +02:00
Julian Hammer
c4163dd930 Merge branch 'master' of github.com:RRZE-HPC/OSACA 2021-04-23 13:18:23 +02:00
Julian
04836cf3f9 Validation (#71)
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.

build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.

For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz

The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb

Quite a few changes on OSACA included:

Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
afa607e546 migrate code style to Black 2021-03-11 12:02:45 +01:00
JanLJL
89aa82f9c8 changed test after adjustment in parser 2021-02-25 08:12:10 +01:00
JanLJL
40afe51454 added the possibility of a 5th operand 2020-12-06 18:05:59 +01:00
JanLJL
2df4b353ed no \t replacement before any other point than user output 2020-10-16 09:44:18 +02:00
JanLJL
fb0ba144a5 adjusted tests for AArch64 2020-10-15 17:56:08 +02:00