Robin Leroy
b7e4acc905
ucomisd is like comisd
2025-03-27 22:46:48 +01:00
pleroy
b989145a36
Define comisd sources.
2025-03-27 22:46:38 +01:00
Robin Leroy
9e6373a013
Configure the dependencies of the jmeow instructions on flags
2025-03-20 22:30:00 +01:00
Robin Leroy
e99c3d935d
Add the setmeow instructions
2025-03-20 22:29:51 +01:00
stefandesouza
07f1af966d
Reverted comment
2024-02-22 13:47:47 +01:00
stefandesouza
4647615c5c
Merge remote-tracking branch 'origin/master' into InstrucForm
2023-12-16 12:14:36 +01:00
JanLJL
c5ef5f7432
bugfixes for SP reg and ccodes
2023-12-12 18:32:43 +01:00
stefandesouza
2c32ccf37a
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
14a2aa0b52
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
JanLJL
0b93766bdd
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
d6569a0f23
renamed condition code attrib, fixed incorrect src/dst, and added more conditional instructions
2023-03-14 16:57:34 +01:00
JanLJL
841a4a5724
resolve #81
2023-03-02 15:50:13 +01:00
Décio Luiz Gazzoni Filho
19c47db3ed
Support for flags and conditional ops on AArch64
2023-02-19 22:08:42 -03:00
JanLJL
2306cb58d0
added more instructions for ICX
2022-09-01 15:49:28 +02:00
JanLJL
671f7f5591
added ICX architecture
2022-08-29 11:14:56 +02:00
Jan
3d26d6b82a
Merge pull request #84 from qcjiang/feature/tsv110
...
Feature/tsv110
2022-04-06 16:25:39 +02:00
JanLJL
75bc03bc76
bugfixes and additions
2022-03-28 10:06:51 +02:00
JanLJL
9c966c2359
small bugfixes
2022-03-17 16:38:28 +01:00
JanLJL
a767b7f290
Closes #78 , closes #79 ; added unary/binary logical operators
2021-11-04 12:09:44 +01:00
JanLJL
b70cff21ad
added instructions for BHIVE
2021-09-29 17:26:44 +02:00
JanLJL
615c809fe3
updated a few DB entries
2021-06-02 16:37:18 +02:00
Julian
08440ed5e1
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
25a0e0607d
added missing instructions to all DBs
2021-04-05 16:47:52 +02:00
JanLJL
8e3d613843
new instructions
2020-12-09 11:52:10 +01:00
JanLJL
b9e434d124
new instructions
2020-12-07 01:18:32 +01:00
JanLJL
f69b5f88f0
removed false entries
2020-11-21 21:02:44 +01:00
Julian
dd59af16b2
Merge pull request #51 from RRZE-HPC/A64FX
...
A64FX support and several Arm bugfixes and enhancements including better TP scheduling
2020-10-16 10:44:47 +02:00
JanLJL
d9325724e2
removed duplicate cmp entry
2020-10-16 10:11:51 +02:00
JanLJL
e8b78e4cc6
Merge branch 'master' into A64FX
2020-10-15 22:44:12 +02:00
Julian Hammer
c80088b628
Merge branch 'master' into fix/increment_handling
2020-10-15 16:36:29 +02:00
Julian Hammer
748474cd81
added more cmp versions
2020-10-15 16:23:14 +02:00
Julian Hammer
cf4a9cddcb
Merge branch 'master' into fix/increment_handling
2020-10-15 13:17:02 +02:00
Julian Hammer
5a5a1e74f5
added CMP to aarch64 to exclude first op from destinations
2020-10-15 13:15:54 +02:00
Julian Hammer
d03398ddf9
treating post- and pre-incremeted memory references no longer as src_dst
...
the incremented register is now considered src_dst instead
2020-10-13 19:25:29 +02:00
Julian Hammer
d6529ced73
fixed push and added pop
2020-10-12 15:03:03 +02:00
JanLJL
accb52ce53
Merge branch 'master' of github.com:RRZE-HPC/osaca
2020-09-17 22:15:20 +02:00
JanLJL
9e78f85475
added instructions
2020-09-17 22:14:14 +02:00
JanLJL
5361b63b52
version bump
2020-08-03 09:38:50 +02:00
JanLJL
93060eee43
Merge branch 'master' into A64FX
2020-07-13 14:41:49 +02:00
JanLJL
ce8c3ff9ab
bugfixes for A64FX
2020-07-06 18:48:54 +02:00
JanLJL
93c1951097
prettified aarch64 ISA DB
2020-06-25 21:54:52 +02:00
JanLJL
94d7d35c0b
more instructions
2020-05-04 18:50:58 +02:00
JanLJL
38924b6ec1
more instructions
2020-03-30 18:27:33 +02:00
JanLJL
17e7f0e0d8
more instruction forms and added wildcard support for registers in ISA DB
2020-03-12 15:07:51 +01:00
JanLJL
3243455ec5
bugfixes and new instructions
2020-01-29 13:04:03 +01:00
JanLJL
2fc1f3a186
added new instructions and fixed false positive assignment of stores by dynamic TP/LT combination for aarch64
2020-01-22 21:40:11 +01:00
JanLJL
1fd2453a50
Merge branch 'master' of github.com:RRZE-HPC/osaca
2020-01-17 16:56:01 +01:00
Julian Hammer
daa566329c
some more instructions (esp. AT&T naming)
2020-01-17 16:30:00 +01:00
JanLJL
b202bdfdb0
Merge branch 'master' of github.com:RRZE-HPC/osaca
2020-01-17 15:19:12 +01:00
JanLJL
534eda8015
added ldur and stur
2020-01-17 15:16:00 +01:00
