JanLJL
2cf2bf5cec
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
4e3994fec1
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
9c2f559983
black formatting
2025-03-05 10:20:47 +01:00
pleroy
1a7c1588f6
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
aca5511d6a
Black formatting
2024-05-02 17:04:56 +02:00
stefandesouza
1c0708e750
Added updated files
2024-02-27 14:47:55 +01:00
stefandesouza
ec798f61b2
More formatting
2024-01-10 13:26:50 +01:00
stefandesouza
339b06bd7f
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
8a6ae8c701
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
cac4a0ebf2
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
cef7f8098d
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
93ae586745
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
2c32ccf37a
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
26d65750a6
Fixed issue with throughput assignment
2023-10-30 19:32:05 +01:00
stefandesouza
ebb973493b
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
14a2aa0b52
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
33d1eec106
Updated tests to use the now class style iforms in isa_data
2023-10-23 16:25:31 +02:00
stefandesouza
e95278d2a2
Included 'source' and 'destination' attributes when loading isa data
2023-10-16 15:48:47 +02:00
stefandesouza
db899a2709
Changing operand matching for class operand style
2023-09-25 21:35:17 +02:00
stefandesouza
42f96753c1
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
a8e5a6ad46
Converting operand types read in from YAML files
2023-09-12 00:23:59 +02:00
stefandesouza
7f4f87d192
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
615ef82f04
Changes to accomodate the new OO style
2023-08-28 15:19:46 +02:00
stefandesouza
0a32c77751
Added 2 operand types and made changes for attribute usage
2023-08-20 21:01:44 +02:00
stefan.desouza@outlook.com
1eb692c86f
Classes for OperandForm and Operand types
2023-08-07 15:01:48 +02:00
JanLJL
0b93766bdd
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
d1201ace11
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
f06f767c34
formatting according to black
2023-03-03 15:24:18 +01:00
JanLJL
9f715c0ba3
added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes
2023-03-03 15:11:40 +01:00
JanLJL
9c966c2359
small bugfixes
2022-03-17 16:38:28 +01:00
JanLJL
5205cb5cc6
fixed formatting with correct line length
2021-10-04 15:00:17 +02:00
JanLJL
566fbc6bc4
black conformity
2021-09-30 15:53:56 +02:00
JanLJL
d181184788
enhanced parser
2021-09-29 17:26:27 +02:00
JanLJL
d418c16f4a
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
d59b100fa8
changed immediate type from str to int
2021-05-10 01:12:30 +02:00
Julian Hammer
1f32252f91
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
08440ed5e1
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
6204c90934
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
9d2ea8603f
new caching structure with support for distribution
2020-10-28 16:29:55 +01:00
Julian
dd59af16b2
Merge pull request #51 from RRZE-HPC/A64FX
...
A64FX support and several Arm bugfixes and enhancements including better TP scheduling
2020-10-16 10:44:47 +02:00
Julian Hammer
d03398ddf9
treating post- and pre-incremeted memory references no longer as src_dst
...
the incremented register is now considered src_dst instead
2020-10-13 19:25:29 +02:00
JanLJL
6c72281d65
prepared for aarch64 8.2 support
2020-07-23 15:54:54 +02:00
JanLJL
0e77b7bc9a
enhanced TP scheduling
2020-07-06 18:49:46 +02:00
JanLJL
666512d54d
added reg-only fallback for mem-instructions not found in ISA DB
2020-03-10 17:15:57 +01:00
JanLJL
4e73e24b99
added documentation
2020-03-09 16:35:06 +01:00
JanLJL
76469f7898
supports hidden operands now (for flags or special instructions)
2020-01-14 20:54:00 +01:00
JanLJL
cafe4c5bf8
adjusted for mem wildcards in AArch64 ISA DB
2020-01-10 14:38:17 +01:00
JanLJL
3ca2586bac
added --ignore-unknown flag and major updates in x86 parser
2020-01-09 17:57:08 +01:00
Julian Hammer
f18a48653f
FIX #46 untangled semantic and non-semantic operand info
2019-11-14 16:43:33 +01:00
Julian Hammer
a91413c270
added list processing function
2019-10-30 09:31:01 +01:00
