135 Commits

Author	SHA1	Message	Date
stefandesouza	d4a6a9b44f	Instruction form text change	2024-02-22 13:49:56 +01:00
stefandesouza	04388af5dd	Made all attributes lower case	2024-02-22 13:48:56 +01:00
stefandesouza	1fb015b312	Formatting before PR	2024-01-10 13:05:27 +01:00
stefandesouza	226bc8eee0	Added shift and shift_op to Register Operand	2024-01-04 14:34:36 +01:00
stefandesouza	0b3508abf8	Small cleaup commit	2023-12-16 16:00:37 +01:00
stefandesouza	4647615c5c	Merge remote-tracking branch 'origin/master' into InstrucForm	2023-12-16 12:14:36 +01:00
JanLJL	c5ef5f7432	bugfixes for SP reg and ccodes	2023-12-12 18:32:43 +01:00
stefandesouza	339b06bd7f	Linters update	2023-12-10 18:25:00 +01:00
stefandesouza	8a6ae8c701	Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes	2023-12-10 17:26:43 +01:00
stefandesouza	cac4a0ebf2	flake8 standards	2023-12-03 21:04:58 +01:00
stefandesouza	cef7f8098d	Black formatting	2023-12-03 17:22:11 +01:00
stefandesouza	93ae586745	Fixed semantic and marker tests. Now only dump needs to be adjusted	2023-12-03 16:49:33 +01:00
stefandesouza	2c32ccf37a	pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also	2023-12-02 16:56:43 +01:00
stefandesouza	ebb973493b	Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working	2023-10-29 16:36:00 +01:00
stefandesouza	14a2aa0b52	Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class	2023-10-29 13:52:49 +01:00
stefandesouza	4186edbc03	added a couple of attributes	2023-10-23 21:57:01 +02:00
stefandesouza	e95278d2a2	Included 'source' and 'destination' attributes when loading isa data	2023-10-16 15:48:47 +02:00
stefandesouza	0b2753a78d	Throughput assignment adjustments	2023-09-25 23:20:10 +02:00
stefandesouza	42f96753c1	Black formatting	2023-09-12 12:45:28 +02:00
stefandesouza	a8e5a6ad46	Converting operand types read in from YAML files	2023-09-12 00:23:59 +02:00
stefandesouza	7f4f87d192	Changes for operand matching, instruction loading	2023-09-11 18:23:57 +02:00
stefandesouza	615ef82f04	Changes to accomodate the new OO style	2023-08-28 15:19:46 +02:00
stefandesouza	36549dd679	Updated list/range register resolver & applied black formatting	2023-08-26 14:51:04 +02:00
stefandesouza	76f3baf74e	Removed all AttrDict() usage in parser. process_operand() now turns single registers into operands	2023-08-21 18:53:56 +02:00
stefandesouza	b06e6424f7	Added eq methods, changed AArch parser tests for class usage	2023-08-21 15:36:40 +02:00
stefandesouza	0a32c77751	Added 2 operand types and made changes for attribute usage	2023-08-20 21:01:44 +02:00
stefandesouza	eb09cbde42	Module imports	2023-08-20 13:37:57 +02:00
stefandesouza	ecdfc15ac5	InstrucForm class usage in AArch parser	2023-08-20 13:35:11 +02:00
stefandesouza	317816b9d3	Separate operand files with inheritance, str and repr classes	2023-08-20 12:10:07 +02:00
stefandesouza	4c74bb0d46	Merge remote-tracking branch 'origin/master' into InstrucForm ... merge	2023-08-20 11:39:20 +02:00
stefandesouza	537076fa25	Added seperate operand class files	2023-08-20 11:38:56 +02:00
JanLJL	ab10febe74	enhanced YAML output to include all kernel objects and no ruamel.yaml-specific data types	2023-08-15 14:01:11 +02:00
stefan.desouza@outlook.com	1eb692c86f	Classes for OperandForm and Operand types	2023-08-07 15:01:48 +02:00
stefan.desouza@outlook.com	9a0474bcc1	Added DirectiveClass with comment iterator	2023-08-06 17:42:42 +02:00
stefan.desouza@outlook.com	71e2931bb0	Added InstructionForm class	2023-08-06 17:13:42 +02:00
JanLJL	54644ffb09	black-compliant formatting	2023-03-14 18:22:27 +01:00
JanLJL	0b93766bdd	Merge branch 'master' into pr-armcc	2023-03-14 17:50:48 +01:00
JanLJL	d1201ace11	added more dependency analysis for post/pre indexing and condition flags	2023-03-14 17:00:02 +01:00
JanLJL	2884d17971	enabled indexing without shape and lane for vector regs	2023-03-03 14:41:48 +01:00
Décio Luiz Gazzoni Filho	19c47db3ed	Support for flags and conditional ops on AArch64	2023-02-19 22:08:42 -03:00
JanLJL	93c0753db3	formatting	2022-04-07 12:17:08 +02:00
Qingcai Jiang	fa06b9ccac	fix a bug about orr in tsv110	2022-03-20 14:53:34 +08:00
Jan	2be8606e9a	black-conform formatting	2021-12-03 14:38:52 +01:00
Qingcai Jiang	d170ba72dd	fix a bug when the hex_number of address is negative	2021-12-03 15:13:54 +08:00
JanLJL	d181184788	enhanced parser	2021-09-29 17:26:27 +02:00
JanLJL	d418c16f4a	applied flake8 and black rules	2021-08-26 16:58:19 +02:00
JanLJL	090c24ade1	fixed parsing of reg ranges and lists	2021-06-01 00:10:05 +02:00
JanLJL	d59b100fa8	changed immediate type from str to int	2021-05-10 01:12:30 +02:00
JanLJL	66282b0eef	fix #73	2021-05-02 22:22:30 +02:00
Julian Hammer	1f32252f91	improved register range and list support on AArch64	2021-04-23 13:12:18 +02:00