stefandesouza
e253638cb7
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
4ec3788f58
Dump now converts classes to dicts
2024-03-05 00:18:45 +01:00
stefandesouza
62c21a7f31
Port pressure returned in tuple with Memory Operand
2024-03-04 20:00:43 +01:00
stefandesouza
d944c82d33
Immediate operand attribute name changes
2024-02-28 13:01:37 +01:00
stefandesouza
6ce910e779
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
stefandesouza
d7768e5a8a
Removed comments from operands
2024-02-24 14:15:25 +01:00
stefandesouza
9a7f38396f
Formatting before PR
2024-01-10 13:05:27 +01:00
stefandesouza
a2c67f1a61
Added shift and shift_op to Register Operand
2024-01-04 14:34:36 +01:00
stefandesouza
de6d8a1197
Small cleaup commit
2023-12-16 16:00:37 +01:00
stefandesouza
b8e88f9319
Merge remote-tracking branch 'origin/master' into InstrucForm
2023-12-16 12:14:36 +01:00
JanLJL
b7ff0b1461
bugfixes for SP reg and ccodes
2023-12-12 18:32:43 +01:00
stefandesouza
405a1d2857
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
47a44c9865
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
1885ce6ddb
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
78ca6fe855
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
cce05e44cb
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
166071bbb1
Throughput assignment adjustments
2023-09-25 23:20:10 +02:00
stefandesouza
2f8c2f56cf
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
14ecefd677
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
72a17ac8c8
Updated list/range register resolver & applied black formatting
2023-08-26 14:51:04 +02:00
stefandesouza
47b8dba572
Removed all AttrDict() usage in parser. process_operand() now turns single registers into operands
2023-08-21 18:53:56 +02:00
stefandesouza
9d54b4da47
Added eq methods, changed AArch parser tests for class usage
2023-08-21 15:36:40 +02:00
stefandesouza
5ca37a2a3f
Added 2 operand types and made changes for attribute usage
2023-08-20 21:01:44 +02:00
stefandesouza
17ef6582d1
InstrucForm class usage in AArch parser
2023-08-20 13:35:11 +02:00
JanLJL
261039e51e
black-compliant formatting
2023-03-14 18:22:27 +01:00
JanLJL
97756faa04
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
0985e81b23
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
c1373fe44c
enabled indexing without shape and lane for vector regs
2023-03-03 14:41:48 +01:00
Décio Luiz Gazzoni Filho
b434e30ec1
Support for flags and conditional ops on AArch64
2023-02-19 22:08:42 -03:00
JanLJL
9bbb289f9d
formatting
2022-04-07 12:17:08 +02:00
Qingcai Jiang
728bb03a93
fix a bug about orr in tsv110
2022-03-20 14:53:34 +08:00
Jan
b18f7bf718
black-conform formatting
2021-12-03 14:38:52 +01:00
Qingcai Jiang
3efda4ba6c
fix a bug when the hex_number of address is negative
2021-12-03 15:13:54 +08:00
JanLJL
1b40c10a1f
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
ec771dbe91
fixed parsing of reg ranges and lists
2021-06-01 00:10:05 +02:00
JanLJL
5038ce7a15
changed immediate type from str to int
2021-05-10 01:12:30 +02:00
Julian Hammer
781b8b6b89
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
04836cf3f9
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
afa607e546
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
c788e7b97b
passing parsing errors to the outside
2021-03-05 18:07:36 +01:00
JanLJL
70ddce85c9
fixed AArch64 parser for register shifts and new instructions for A64FX
2021-02-25 07:43:42 +01:00
JanLJL
c783b2ce2d
enhancements for lookup and parsing AArch64 instrs
2020-12-07 01:18:32 +01:00
JanLJL
40afe51454
added the possibility of a 5th operand
2020-12-06 18:05:59 +01:00
JanLJL
e643520a79
replaced 582b46b3 with smarter solution
2020-11-20 15:44:49 +01:00
JanLJL
582b46b347
bugfix for immediate shifts with hex-base
2020-11-20 15:22:05 +01:00
Julian Hammer
0e4d5a6692
singelton for isa parsers
2020-11-09 12:36:14 +01:00
JanLJL
aa6252f270
bugfixes
2020-11-06 12:03:54 +01:00
