5 Commits

Author	SHA1	Message	Date
Metehan Dundar	ebf76caa18	Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames ... - Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support - Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.) - Renamed example files from rv6 to rv64 for consistency - Updated related configuration and test files - All 115 tests pass successfully	2025-07-11 18:15:51 +02:00
Metehan Dundar	61b52dbf28	RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests ... - Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples	2025-06-30 00:28:52 +02:00
Metehan Dundar	d782f06e84	Add RISC-V support and update version to 0.6.2	2025-03-21 17:16:39 +01:00
Metehan Dundar	653c27135d	Add initial support for RISC-V architecture and update relevant files	2025-03-11 05:10:03 +01:00
Metehan Dundar	7e546d970f	Parser for RISCV is implemented and tested with a ... simple kernel. Changes to be committed: modified: osaca/parser/__init__.py new file: osaca/parser/parser_RISCV.py new file: tests/test_files/kernel_riscv.s new file: tests/test_parser_RISCV.py	2025-03-04 00:44:38 +01:00