JanLJL
fb7f1a289d
flake8 formatting
2025-03-05 10:19:10 +01:00
JanLJL
a4939d1873
renamed .asm files to .s for consistency
2025-03-05 09:36:07 +01:00
pleroy
b4d342266d
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
2e29f0b4e1
moved get_full_instruction_name() from HardwareModel to DBInterface
2024-05-02 16:25:41 +02:00
stefandesouza
e253638cb7
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
0474148d7b
Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples
2024-02-24 21:03:15 +01:00
stefandesouza
33ad20dc3a
More formatting
2024-01-10 13:26:50 +01:00
stefandesouza
1885ce6ddb
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
e77dfb4eb3
Fixed issue with throughput assignment
2023-10-30 19:32:05 +01:00
stefandesouza
78ca6fe855
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
cce05e44cb
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
a11d0f1845
Hidden operands and dependency break in iforms now included
2023-10-23 21:54:58 +02:00
stefandesouza
17cd1a70c7
Updated tests to use the now class style iforms in isa_data
2023-10-23 16:25:31 +02:00
stefandesouza
d81a8df7e7
Convert isa_data iforms to InstructionForm type
2023-10-17 12:28:49 +02:00
stefandesouza
fad1997b76
Included 'source' and 'destination' attributes when loading isa data
2023-10-16 15:48:47 +02:00
stefandesouza
166071bbb1
Throughput assignment adjustments
2023-09-25 23:20:10 +02:00
stefandesouza
bc058233a3
Changing operand matching for class operand style
2023-09-25 21:35:17 +02:00
stefandesouza
2f8c2f56cf
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
a761ee43f1
Converting operand types read in from YAML files
2023-09-12 00:23:59 +02:00
stefandesouza
14ecefd677
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
0f182551f2
Changes to accomodate the new OO style
2023-08-28 15:19:46 +02:00
JanLJL
261039e51e
black-compliant formatting
2023-03-14 18:22:27 +01:00
JanLJL
97756faa04
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
0985e81b23
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
23139d4d5b
bugfix, resolved #90
2023-03-07 17:05:31 +01:00
JanLJL
72f69fa707
added fallback search in arch/ISA model for ARM instructions with shape/cc suffixes
2023-03-03 15:11:40 +01:00
JanLJL
d5aaceb9c4
added Zen3 support
2022-09-27 18:39:14 +02:00
JanLJL
1b40c10a1f
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
8e09927178
added tests for timeout in LCD analyis
2021-05-02 22:48:22 +02:00
Julian Hammer
781b8b6b89
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
04836cf3f9
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
0f8e53e918
making flake8 happy
2021-03-11 12:29:14 +01:00
Julian Hammer
afa607e546
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
7f8b596fc9
improved performance of arch_semantics and reg dependency matching
2020-11-09 19:27:47 +01:00
Julian Hammer
e29cfb3185
new caching structure with support for distribution
2020-10-28 16:29:55 +01:00
JanLJL
fb0ba144a5
adjusted tests for AArch64
2020-10-15 17:56:08 +02:00
JanLJL
a204762fa3
enabled kerncraft marker insertion for aarch64 and more tests
2020-02-27 16:00:23 +01:00
JanLJL
aa0603860b
running examples for tests
2020-02-26 18:40:08 +01:00
JanLJL
b43a962d66
more tests
2020-02-26 17:32:13 +01:00
JanLJL
6776be5c5d
added test for optimal throughput assignment and invalid asmbench import files
2020-02-20 16:34:11 +01:00
JanLJL
ee6ed33aac
added tests for asmbench import
2020-02-20 12:07:20 +01:00
JanLJL
17018ac6ad
made detection of flag dependencies as opt_in for now
2020-01-29 13:03:43 +01:00
JanLJL
15782bd106
added comment line marker support and adjusted tests
2020-01-22 15:06:56 +01:00
JanLJL
1a089ccf76
adjusted test due to hidden operand dependencies
2020-01-17 08:13:15 +01:00
Julian Hammer
63ca1e66bf
FIX #46 untangled semantic and non-semantic operand info
2019-11-14 16:43:33 +01:00
JanLJL
d1204f7e9d
separated SemanticsAppender into ISA and Arch semantics
2019-10-29 09:09:52 +01:00
JanLJL
077de5cb42
changed DBs to new port_pressure structure
2019-10-16 10:06:47 +02:00
