mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-04 10:10:08 +01:00
61b52dbf28
- Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples
24 lines
547 B
Python
Executable File
24 lines
547 B
Python
Executable File
#!/usr/bin/env python3
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import sys
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import unittest
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sys.path[0:0] = [".", ".."]
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suite = unittest.TestLoader().loadTestsFromNames(
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[
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"test_base_parser",
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"test_parser_x86att",
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"test_parser_x86intel",
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"test_parser_AArch64",
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"test_parser_RISCV",
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"test_marker_utils",
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"test_semantics",
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"test_frontend",
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"test_db_interface",
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"test_cli",
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]
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)
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testresult = unittest.TextTestRunner(verbosity=2, buffer=True).run(suite)
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sys.exit(0 if testresult.wasSuccessful() else 1)
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