JanLJL bc91ab3b70 Merge branch 'master' of github.com:RRZE-HPC/OSACA

2026-01-23 12:42:27 +01:00

..

__init__.py

Merge branch 'master' into merge-branch

2025-03-07 14:45:44 +01:00

base_parser.py

add syntax property for parsers and fix bug for VEX/non-VEX replacement

2026-01-22 17:26:03 +01:00

condition.py

fixed imprecise operand comparison

2026-01-14 11:08:53 +01:00

directive.py

Black formatting

2024-03-05 12:14:05 +01:00

flag.py

Black formatting

2024-03-05 12:14:05 +01:00

identifier.py

Add support for the Intel syntax supported by MSVC and ICC

2025-02-02 14:02:16 +01:00

immediate.py

Flake8 formatting

2024-05-02 17:00:12 +02:00

instruction_form.py

formatting

2026-01-13 11:14:47 +01:00

label.py

Add support for the Intel syntax supported by MSVC and ICC

2025-02-02 14:02:16 +01:00

memory.py

Add support for the Intel syntax supported by MSVC and ICC

2025-02-02 14:02:16 +01:00

operand.py

Took out name attribute from operand parent class

2024-02-24 15:46:04 +01:00

parser_AArch64.py

add syntax property for parsers and fix bug for VEX/non-VEX replacement

2026-01-22 17:26:03 +01:00

parser_x86.py

Add support for the Intel syntax supported by MSVC and ICC

2025-02-02 14:02:16 +01:00

parser_x86att.py

add syntax property for parsers and fix bug for VEX/non-VEX replacement

2026-01-22 17:26:03 +01:00

parser_x86intel.py

Merge branch 'master' of github.com:RRZE-HPC/OSACA

2026-01-23 12:42:27 +01:00

prefetch.py

fixed imprecise operand comparison

2026-01-14 11:08:53 +01:00

register.py

fixed bugs in x86intel parser (ZMM and masking support)

2025-09-08 16:35:36 +02:00