mirror of
https://github.com/RRZE-HPC/OSACA.git
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722 lines
30 KiB
Python
722 lines
30 KiB
Python
#!/usr/bin/env python3
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from copy import deepcopy
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import pyparsing as pp
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from osaca.parser import BaseParser
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from osaca.parser.instruction_form import InstructionForm
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from osaca.parser.operand import Operand
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from osaca.parser.directive import DirectiveOperand
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.label import LabelOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser.identifier import IdentifierOperand
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from osaca.parser.immediate import ImmediateOperand
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from osaca.parser.condition import ConditionOperand
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from osaca.parser.prefetch import PrefetchOperand
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from osaca.semantics.hw_model import MachineModel
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class ParserAArch64(BaseParser):
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_instance = None
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# Singelton pattern, as this is created very many times
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def __new__(cls):
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if cls._instance is None:
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cls._instance = super(ParserAArch64, cls).__new__(cls)
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return cls._instance
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def __init__(self):
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super().__init__()
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def isa(self):
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return "aarch64"
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def start_marker(self):
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return [
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InstructionForm(
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mnemonic="mov",
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operands=[RegisterOperand(name="1", prefix="x"), ImmediateOperand(value=111)]
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),
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InstructionForm(
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directive_id=DirectiveOperand(name="byte", parameters=["213", "3", "32", "31"])
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)
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]
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def end_marker(self):
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return [
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InstructionForm(
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mnemonic="mov",
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operands=[RegisterOperand(name="1", prefix="x"), ImmediateOperand(value=222)]
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),
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InstructionForm(
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directive_id=DirectiveOperand(name="byte", parameters=["213", "3", "32", "31"])
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)
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]
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def normalize_instruction_form(
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self,
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instruction_form,
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isa_model: MachineModel,
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arch_model: MachineModel
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):
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"""
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If the instruction doesn't exist in the machine model, normalize it by dropping the shape
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suffix.
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"""
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if instruction_form.normalized:
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return
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instruction_form.normalized = True
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mnemonic = instruction_form.mnemonic
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if not mnemonic:
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return
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model = arch_model.get_instruction(mnemonic, instruction_form.operands)
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if not model:
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if "." in mnemonic:
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# Check for instruction without shape/cc suffix.
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suffix_start = mnemonic.index(".")
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mnemonic = mnemonic[:suffix_start]
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model = arch_model.get_instruction(mnemonic, instruction_form.operands)
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if model:
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instruction_form.mnemonic = mnemonic
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def construct_parser(self):
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"""Create parser for ARM AArch64 ISA."""
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# Comment
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symbol_comment = "//"
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self.comment = pp.Literal(symbol_comment) + pp.Group(
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pp.ZeroOrMore(pp.Word(pp.printables))
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).setResultsName(self.comment_id)
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# Define ARM assembly identifier
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decimal_number = pp.Combine(
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pp.Optional(pp.Literal("-")) + pp.Word(pp.nums)
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).setResultsName("value")
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hex_number = pp.Combine(
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pp.Optional(pp.Literal("-")) + pp.Literal("0x") + pp.Word(pp.hexnums)
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).setResultsName("value")
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relocation = pp.Combine(pp.Literal(":") + pp.Word(pp.alphanums + "_") + pp.Literal(":"))
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first = pp.Word(pp.alphas + "_.", exact=1)
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rest = pp.Word(pp.alphanums + "_.")
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identifier = pp.Group(
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pp.Optional(relocation).setResultsName("relocation")
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+ pp.Combine(first + pp.Optional(rest)).setResultsName("name")
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+ pp.Optional(
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pp.Suppress(pp.Literal("+"))
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+ (hex_number | decimal_number).setResultsName("offset")
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)
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).setResultsName(self.identifier)
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# Label
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self.label = pp.Group(
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identifier.setResultsName("name") + pp.Literal(":") + pp.Optional(self.comment)
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).setResultsName(self.label_id)
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# Directive
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directive_option = pp.Combine(
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pp.Word(pp.alphas + "#@.%", exact=1)
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+ pp.Optional(pp.Word(pp.printables + " ", excludeChars=","))
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)
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directive_parameter = (
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pp.quotedString | directive_option | identifier | hex_number | decimal_number
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)
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commaSeparatedList = pp.delimitedList(pp.Optional(directive_parameter), delim=",")
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self.directive = pp.Group(
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pp.Literal(".")
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+ pp.Word(pp.alphanums + "_").setResultsName("name")
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+ (pp.OneOrMore(directive_parameter) ^ commaSeparatedList).setResultsName("parameters")
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+ pp.Optional(self.comment)
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).setResultsName(self.directive_id)
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# LLVM-MCA markers
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self.llvm_markers = pp.Group(
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pp.Literal("#")
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+ pp.Combine(
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pp.CaselessLiteral("LLVM-MCA-")
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+ (pp.CaselessLiteral("BEGIN") | pp.CaselessLiteral("END"))
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)
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+ pp.Optional(self.comment)
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).setResultsName(self.comment_id)
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##############################
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# Instructions
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# Mnemonic
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# (?P<instr>[a-zA-Z][a-zA-Z0-9]*)(?P<setflg>S?)(P?<CC>.[a-zA-Z]{2})
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mnemonic = pp.Word(pp.alphanums + ".").setResultsName("mnemonic")
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# Immediate:
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# int: ^-?[0-9]+ | hex: ^0x[0-9a-fA-F]+ | fp: ^[0-9]{1}.[0-9]+[eE]{1}[\+-]{1}[0-9]+[fF]?
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symbol_immediate = "#"
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mantissa = pp.Combine(
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pp.Optional(pp.Literal("-")) + pp.Word(pp.nums) + pp.Literal(".") + pp.Word(pp.nums)
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).setResultsName("mantissa")
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exponent = (
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pp.CaselessLiteral("e")
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+ pp.Word("+-").setResultsName("e_sign")
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+ pp.Word(pp.nums).setResultsName("exponent")
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)
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float_ = pp.Group(
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mantissa + pp.Optional(exponent) + pp.CaselessLiteral("f")
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).setResultsName("float")
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double_ = pp.Group(mantissa + pp.Optional(exponent)).setResultsName("double")
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immediate = pp.Group(
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pp.Optional(pp.Literal(symbol_immediate))
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+ (hex_number ^ decimal_number ^ float_ ^ double_)
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| (pp.Optional(pp.Literal(symbol_immediate)) + identifier)
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).setResultsName(self.immediate_id)
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shift_op = (
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pp.CaselessLiteral("lsl")
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^ pp.CaselessLiteral("lsr")
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^ pp.CaselessLiteral("asr")
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^ pp.CaselessLiteral("ror")
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^ pp.CaselessLiteral("sxtw")
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^ pp.CaselessLiteral("uxtw")
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^ pp.CaselessLiteral("uxtb")
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^ pp.CaselessLiteral("mul vl")
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)
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arith_immediate = pp.Group(
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immediate.setResultsName("base_immediate")
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+ pp.Suppress(pp.Literal(","))
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+ shift_op.setResultsName("shift_op")
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+ pp.Optional(immediate).setResultsName("shift")
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).setResultsName(self.immediate_id)
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# Register:
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# scalar: [XWBHSDQ][0-9]{1,2} | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])?
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# | predicate: P[0-9]{1,2}(/[ZM])?
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# ignore vector len control ZCR_EL[123] for now
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# define SP, ZR register aliases as regex, due to pyparsing does not support
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# proper lookahead
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alias_r31_sp = pp.Regex("(?P<prefix>[a-zA-Z])?(?P<name>(sp|SP))")
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alias_r31_zr = pp.Regex("(?P<prefix>[a-zA-Z])?(?P<name>(zr|ZR))")
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scalar = pp.Word("xwbhsdqXWBHSDQ", exact=1).setResultsName("prefix") + pp.Word(
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pp.nums
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).setResultsName("name")
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index = pp.Literal("[") + pp.Word(pp.nums).setResultsName("index") + pp.Literal("]")
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vector = (
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pp.oneOf("v z", caseless=True).setResultsName("prefix")
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+ pp.Word(pp.nums).setResultsName("name")
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+ pp.Optional(
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pp.Literal(".")
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+ pp.Optional(pp.Word("12468")).setResultsName("lanes")
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+ pp.Word(pp.alphas, exact=1).setResultsName("shape")
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)
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+ pp.Optional(index)
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)
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predicate = (
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pp.CaselessLiteral("p").setResultsName("prefix")
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+ pp.Word(pp.nums).setResultsName("name")
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+ pp.Optional(
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(
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pp.Suppress(pp.Literal("/"))
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+ pp.oneOf("z m", caseless=True).setResultsName("predication")
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)
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| (
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pp.Literal(".")
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+ pp.Optional(pp.Word("12468")).setResultsName("lanes")
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+ pp.Word(pp.alphas, exact=1).setResultsName("shape")
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)
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)
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)
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self.list_element = vector ^ scalar
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register_list = (
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pp.Literal("{")
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+ (
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pp.delimitedList(pp.Combine(self.list_element), delim=",").setResultsName("list")
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^ pp.delimitedList(pp.Combine(self.list_element), delim="-").setResultsName(
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"range"
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)
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)
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+ pp.Literal("}")
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+ pp.Optional(index)
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)
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register = pp.Group(
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(alias_r31_sp | alias_r31_zr | vector | scalar | predicate | register_list)
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# (alias_r31_sp | alias_r31_zr | vector | scalar | predicate | register_list)
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+ pp.Optional(
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pp.Suppress(pp.Literal(","))
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+ shift_op.setResultsName("shift_op")
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+ pp.Optional(immediate).setResultsName("shift")
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)
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).setResultsName(self.register_id)
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self.register = register
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# Memory
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register_index = register.setResultsName("index") + pp.Optional(
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pp.Literal(",") + pp.Word(pp.alphas) + immediate.setResultsName("scale")
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)
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memory = pp.Group(
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pp.Literal("[")
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+ pp.Optional(register.setResultsName("base"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(register_index ^ (immediate ^ arith_immediate).setResultsName("offset"))
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+ pp.Literal("]")
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+ pp.Optional(
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pp.Literal("!").setResultsName("pre_indexed")
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| (pp.Suppress(pp.Literal(",")) + immediate.setResultsName("post_indexed"))
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)
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).setResultsName(self.memory_id)
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prefetch_op = pp.Group(
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pp.Group(pp.CaselessLiteral("PLD") ^ pp.CaselessLiteral("PST")).setResultsName("type")
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+ pp.Group(
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pp.CaselessLiteral("L1") ^ pp.CaselessLiteral("L2") ^ pp.CaselessLiteral("L3")
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).setResultsName("target")
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+ pp.Group(pp.CaselessLiteral("KEEP") ^ pp.CaselessLiteral("STRM")).setResultsName(
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"policy"
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)
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).setResultsName("prfop")
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# Condition codes, based on http://tiny.cc/armcc
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condition = (
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pp.CaselessLiteral("EQ") # z set
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^ pp.CaselessLiteral("NE") # z clear
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^ pp.CaselessLiteral("CS") # c set
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^ pp.CaselessLiteral("HS") # c set
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^ pp.CaselessLiteral("CC") # c clear
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^ pp.CaselessLiteral("LO") # c clear
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^ pp.CaselessLiteral("MI") # n set
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^ pp.CaselessLiteral("PL") # n clear
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^ pp.CaselessLiteral("VS") # v set
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^ pp.CaselessLiteral("VC") # v clear
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^ pp.CaselessLiteral("HI") # c set and z clear
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^ pp.CaselessLiteral("LS") # c clear or z set
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^ pp.CaselessLiteral("GE") # n and v the same
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^ pp.CaselessLiteral("LT") # n and v different
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^ pp.CaselessLiteral("GT") # z clear, and n and v the same
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^ pp.CaselessLiteral("LE") # z set, or n and v different
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^ pp.CaselessLiteral("AL") # any
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).setResultsName("condition")
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self.condition = condition
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# Combine to instruction form
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operand_first = pp.Group(
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register ^ (prefetch_op | immediate) ^ memory ^ arith_immediate ^ identifier
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)
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operand_rest = pp.Group(
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(register ^ condition ^ immediate ^ memory ^ arith_immediate) | identifier
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)
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self.instruction_parser = (
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mnemonic
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+ pp.Optional(operand_first.setResultsName("operand1"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand_rest.setResultsName("operand2"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand_rest.setResultsName("operand3"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand_rest.setResultsName("operand4"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand_rest.setResultsName("operand5"))
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+ pp.Optional(self.comment)
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)
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# for testing
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self.predicate = predicate
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self.vector = vector
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self.register = register
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def parse_line(self, line, line_number=None):
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"""
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Parse line and return instruction form.
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:param str line: line of assembly code
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:param line_number: identifier of instruction form, defautls to None
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:type line_number: int, optional
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:return: `dict` -- parsed asm line (comment, label, directive or instruction form)
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"""
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instruction_form = InstructionForm(
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mnemonic=None,
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operands=[],
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directive_id=None,
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comment_id=None,
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label_id=None,
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line=line,
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line_number=line_number,
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)
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result = None
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# 1. Parse comment
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try:
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result = self.process_operand(self.comment.parseString(line, parseAll=True).asDict())
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instruction_form.comment = " ".join(result[self.comment_id])
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except pp.ParseException:
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pass
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# 1.2 check for llvm-mca marker
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try:
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result = self.process_operand(
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self.llvm_markers.parseString(line, parseAll=True).asDict()
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)
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instruction_form.comment = " ".join(result[self.comment_id])
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except pp.ParseException:
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pass
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# 2. Parse label
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if result is None:
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try:
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# returns tuple with label operand and comment, if any
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result = self.process_operand(self.label.parseString(line, parseAll=True).asDict())
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instruction_form.label = result[0].name
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if result[1] is not None:
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instruction_form.comment = " ".join(result[1])
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except pp.ParseException:
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pass
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# 3. Parse directive
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if result is None:
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try:
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# returns directive with label operand and comment, if any
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result = self.process_operand(
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self.directive.parseString(line, parseAll=True).asDict()
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)
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instruction_form.directive = DirectiveOperand(
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name=result[0].name, parameters=result[0].parameters
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)
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if result[1] is not None:
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instruction_form.comment = " ".join(result[1])
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except pp.ParseException:
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pass
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# 4. Parse instruction
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if result is None:
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try:
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result = self.parse_instruction(line)
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except (pp.ParseException, KeyError) as e:
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raise ValueError(
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"Unable to parse {!r} on line {}".format(line, line_number)
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) from e
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instruction_form.mnemonic = result.mnemonic
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instruction_form.operands = result.operands
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instruction_form.comment = result.comment
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return instruction_form
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def parse_instruction(self, instruction):
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"""
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Parse instruction in asm line.
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:param str instruction: Assembly line string.
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:returns: `dict` -- parsed instruction form
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"""
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result = self.instruction_parser.parseString(instruction, parseAll=True).asDict()
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operands = []
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# Add operands to list
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# Check first operand
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if "operand1" in result:
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operand = self.process_operand(result["operand1"])
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operands.extend(operand) if isinstance(operand, list) else operands.append(operand)
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# Check second operand
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if "operand2" in result:
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operand = self.process_operand(result["operand2"])
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operands.extend(operand) if isinstance(operand, list) else operands.append(operand)
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# Check third operand
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if "operand3" in result:
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operand = self.process_operand(result["operand3"])
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operands.extend(operand) if isinstance(operand, list) else operands.append(operand)
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# Check fourth operand
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if "operand4" in result:
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operand = self.process_operand(result["operand4"])
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operands.extend(operand) if isinstance(operand, list) else operands.append(operand)
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# Check fifth operand
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if "operand5" in result:
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operand = self.process_operand(result["operand5"])
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operands.extend(operand) if isinstance(operand, list) else operands.append(operand)
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return_dict = InstructionForm(
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mnemonic=result["mnemonic"],
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operands=operands,
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comment_id=" ".join(result[self.comment_id]) if self.comment_id in result else None,
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)
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return return_dict
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def process_operand(self, operand):
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"""Post-process operand"""
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# structure memory addresses
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if self.memory_id in operand:
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return self.process_memory_address(operand[self.memory_id])
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# structure register lists
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if self.register_id in operand and (
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"list" in operand[self.register_id] or "range" in operand[self.register_id]
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):
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# resolve ranges and lists
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return self.resolve_range_list(self.process_register_list(operand[self.register_id]))
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if self.register_id in operand and operand[self.register_id]["name"].lower() == "sp":
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return self.process_sp_register(operand[self.register_id])
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# add value attribute to floating point immediates without exponent
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if self.immediate_id in operand:
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return self.process_immediate(operand[self.immediate_id])
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if self.label_id in operand:
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return self.process_label(operand[self.label_id])
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if self.identifier in operand:
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return self.process_identifier(operand[self.identifier])
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if self.register_id in operand:
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return self.process_register_operand(operand[self.register_id])
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if self.directive_id in operand:
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return self.process_directive_operand(operand[self.directive_id])
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if self.condition_id in operand:
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return self.process_condition(operand[self.condition_id])
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if self.prefetch in operand:
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return self.process_prefetch_operand(operand[self.prefetch])
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return operand
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def process_prefetch_operand(self, operand):
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return PrefetchOperand(
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type_id=operand["type"] if "type" in operand else None,
|
|
target=operand["target"] if "target" in operand else None,
|
|
policy=operand["policy"] if "policy" in operand else None,
|
|
)
|
|
|
|
def process_directive_operand(self, operand):
|
|
return (
|
|
DirectiveOperand(
|
|
name=operand["name"],
|
|
parameters=operand["parameters"],
|
|
),
|
|
operand["comment"] if "comment" in operand else None,
|
|
)
|
|
|
|
def process_register_operand(self, operand):
|
|
return RegisterOperand(
|
|
prefix=operand["prefix"].lower(),
|
|
name=operand["name"],
|
|
shape=operand["shape"].lower() if "shape" in operand else None,
|
|
lanes=operand["lanes"] if "lanes" in operand else None,
|
|
index=operand["index"] if "index" in operand else None,
|
|
predication=operand["predication"].lower() if "predication" in operand else None,
|
|
)
|
|
|
|
def process_memory_address(self, memory_address):
|
|
"""Post-process memory address operand"""
|
|
# Remove unnecessarily created dictionary entries during parsing
|
|
offset = memory_address.get("offset", None)
|
|
if isinstance(offset, list) and len(offset) == 1:
|
|
offset = offset[0]
|
|
if offset is not None and "value" in offset:
|
|
offset = ImmediateOperand(value=int(offset["value"], 0))
|
|
if isinstance(offset, dict) and "identifier" in offset:
|
|
offset = self.process_identifier(offset["identifier"])
|
|
base = memory_address.get("base", None)
|
|
index = memory_address.get("index", None)
|
|
scale = 1
|
|
if base is not None and "name" in base and base["name"].lower() == "sp":
|
|
base["prefix"] = "x"
|
|
if index is not None and "name" in index and index["name"].lower() == "sp":
|
|
index["prefix"] = "x"
|
|
if base is not None and "name" in base and base["name"].lower() == "zr":
|
|
base["prefix"] = "x"
|
|
if index is not None and "name" in index and index["name"].lower() == "zr":
|
|
index["prefix"] = "x"
|
|
valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"]
|
|
if "index" in memory_address:
|
|
if "shift" in memory_address["index"]:
|
|
if memory_address["index"]["shift_op"].lower() in valid_shift_ops:
|
|
scale = 2 ** int(memory_address["index"]["shift"][0]["value"])
|
|
if index is not None:
|
|
index = RegisterOperand(
|
|
name=index["name"],
|
|
prefix=index["prefix"] if "prefix" in index else None,
|
|
shift=index["shift"] if "shift" in index else None,
|
|
shift_op=index["shift_op"] if "shift_op" in index else None,
|
|
)
|
|
new_dict = MemoryOperand(
|
|
offset=offset,
|
|
base=RegisterOperand(name=base["name"], prefix=base["prefix"]),
|
|
index=index,
|
|
scale=scale,
|
|
)
|
|
if "pre_indexed" in memory_address:
|
|
new_dict.pre_indexed = True
|
|
if "post_indexed" in memory_address:
|
|
if "value" in memory_address["post_indexed"]:
|
|
new_dict.post_indexed = {"value": int(memory_address["post_indexed"]["value"], 0)}
|
|
else:
|
|
new_dict.post_indexed = memory_address["post_indexed"]
|
|
return new_dict
|
|
|
|
def process_sp_register(self, register):
|
|
"""Post-process stack pointer register"""
|
|
return RegisterOperand(prefix="x", name="sp")
|
|
|
|
def process_condition(self, condition):
|
|
return ConditionOperand(ccode=condition.upper())
|
|
|
|
def resolve_range_list(self, operand):
|
|
"""
|
|
Resolve range or list register operand to list of registers.
|
|
Returns None if neither list nor range
|
|
"""
|
|
if "list" in operand["register"]:
|
|
index = operand["register"].get("index", None)
|
|
range_list = []
|
|
processed_list = []
|
|
for reg in operand["register"]["list"]:
|
|
reg = deepcopy(reg)
|
|
if index is not None:
|
|
reg["index"] = int(index, 0)
|
|
range_list.append(reg)
|
|
for reg in range_list:
|
|
processed_list.append(self.process_register_operand(reg))
|
|
return processed_list
|
|
# return range_list
|
|
elif "range" in operand["register"]:
|
|
base_register = operand["register"]["range"][0]
|
|
index = operand["register"].get("index", None)
|
|
range_list = []
|
|
processed_list = []
|
|
start_name = base_register["name"]
|
|
end_name = operand["register"]["range"][1]["name"]
|
|
for name in range(int(start_name), int(end_name) + 1):
|
|
reg = deepcopy(base_register)
|
|
if index is not None:
|
|
reg["index"] = int(index, 0)
|
|
reg["name"] = str(name)
|
|
range_list.append(reg)
|
|
for reg in range_list:
|
|
processed_list.append(self.process_register_operand(reg))
|
|
return processed_list
|
|
# neither register list nor range, return unmodified
|
|
return operand
|
|
|
|
def process_register_list(self, register_list):
|
|
"""Post-process register lists (e.g., {r0,r3,r5}) and register ranges (e.g., {r0-r7})"""
|
|
# Remove unnecessarily created dictionary entries during parsing
|
|
rlist = []
|
|
dict_name = ""
|
|
if "list" in register_list:
|
|
dict_name = "list"
|
|
if "range" in register_list:
|
|
dict_name = "range"
|
|
for r in register_list[dict_name]:
|
|
rlist.append(self.list_element.parseString(r, parseAll=True).asDict())
|
|
index = register_list.get("index", None)
|
|
new_dict = {dict_name: rlist, "index": index}
|
|
return {self.register_id: new_dict}
|
|
|
|
def process_immediate(self, immediate):
|
|
"""Post-process immediate operand"""
|
|
dict_name = ""
|
|
if "identifier" in immediate:
|
|
# actually an identifier, change declaration
|
|
return self.process_identifier(immediate["identifier"])
|
|
if "value" in immediate:
|
|
# normal integer value
|
|
immediate["type"] = "int"
|
|
# convert hex/bin immediates to dec
|
|
new_immediate = ImmediateOperand(imd_type=immediate["type"], value=immediate["value"])
|
|
new_immediate.value = self.normalize_imd(new_immediate)
|
|
return new_immediate
|
|
if "base_immediate" in immediate:
|
|
# arithmetic immediate, add calculated value as value
|
|
immediate["shift"] = immediate["shift"][0]
|
|
temp_immediate = ImmediateOperand(value=immediate["base_immediate"]["value"])
|
|
immediate["type"] = "int"
|
|
new_immediate = ImmediateOperand(
|
|
imd_type=immediate["type"], value=None, shift=immediate["shift"]
|
|
)
|
|
new_immediate.value = self.normalize_imd(temp_immediate) << int(
|
|
immediate["shift"]["value"]
|
|
)
|
|
return new_immediate
|
|
if "float" in immediate:
|
|
dict_name = "float"
|
|
if "double" in immediate:
|
|
dict_name = "double"
|
|
if "exponent" in immediate[dict_name]:
|
|
immediate["type"] = dict_name
|
|
return ImmediateOperand(imd_type=immediate["type"], value=immediate[immediate["type"]])
|
|
else:
|
|
# change 'mantissa' key to 'value'
|
|
return ImmediateOperand(value=immediate[dict_name]["mantissa"], imd_type=dict_name)
|
|
|
|
def process_label(self, label):
|
|
"""Post-process label asm line"""
|
|
# remove duplicated 'name' level due to identifier
|
|
return (
|
|
LabelOperand(name=label["name"]["name"]),
|
|
label["comment"] if self.comment_id in label else None,
|
|
)
|
|
|
|
def process_identifier(self, identifier):
|
|
"""Post-process identifier operand"""
|
|
return IdentifierOperand(
|
|
name=identifier["name"] if "name" in identifier else None,
|
|
offset=identifier["offset"] if "offset" in identifier else None,
|
|
relocation=identifier["relocation"] if "relocation" in identifier else None,
|
|
)
|
|
|
|
def get_full_reg_name(self, register):
|
|
"""Return one register name string including all attributes"""
|
|
name = register.prefix + str(register.name)
|
|
if register.shape is not None:
|
|
name += (
|
|
"." + str(register.lanes if register.lanes is not None else "") + register.shape
|
|
)
|
|
if register.index is not None:
|
|
name += "[" + str(register.index) + "]"
|
|
return name
|
|
|
|
def get_regular_source_operands(self, instruction_form):
|
|
"""Get source operand of given instruction form assuming regular src/dst behavior."""
|
|
# if there is only one operand, assume it is a source operand
|
|
if len(instruction_form.operands) == 1:
|
|
return [instruction_form.operands[0]]
|
|
return [op for op in instruction_form.operands[1:]]
|
|
|
|
def get_regular_destination_operands(self, instruction_form):
|
|
"""Get destination operand of given instruction form assuming regular src/dst behavior."""
|
|
# if there is only one operand, assume no destination
|
|
if len(instruction_form.operands) == 1:
|
|
return []
|
|
# return first operand
|
|
return instruction_form.operands[:1]
|
|
|
|
def normalize_imd(self, imd):
|
|
"""Normalize immediate to decimal based representation"""
|
|
if isinstance(imd, IdentifierOperand):
|
|
return imd
|
|
if imd.value is not None and imd.imd_type == "float":
|
|
return self.ieee_to_float(imd.value)
|
|
elif imd.value is not None and imd.imd_type == "double":
|
|
return self.ieee_to_float(imd.value)
|
|
elif imd.value is not None:
|
|
if isinstance(imd.value, str):
|
|
# hex or bin, return decimal
|
|
return int(imd.value, 0)
|
|
else:
|
|
return imd.value
|
|
# identifier
|
|
return imd
|
|
|
|
def ieee_to_float(self, ieee_val):
|
|
"""Convert IEEE representation to python float"""
|
|
exponent = int(ieee_val["exponent"], 10)
|
|
if ieee_val["e_sign"] == "-":
|
|
exponent *= -1
|
|
return float(ieee_val["mantissa"]) * (10**exponent)
|
|
|
|
def parse_register(self, register_string):
|
|
raise NotImplementedError
|
|
|
|
def is_gpr(self, register):
|
|
"""Check if register is a general purpose register"""
|
|
if register.prefix in "wx":
|
|
return True
|
|
return False
|
|
|
|
def is_vector_register(self, register):
|
|
"""Check if register is a vector register"""
|
|
if register.prefix in "bhsdqvz":
|
|
return True
|
|
return False
|
|
|
|
def is_flag_dependend_of(self, flag_a, flag_b):
|
|
"""Check if ``flag_a`` is dependent on ``flag_b``"""
|
|
# we assume flags are independent of each other, e.g., CF can be read while ZF gets written
|
|
# TODO validate this assumption
|
|
return flag_a.name == flag_b.name
|
|
|
|
def is_reg_dependend_of(self, reg_a, reg_b):
|
|
"""Check if ``reg_a`` is dependent on ``reg_b``"""
|
|
# if not isinstance(reg_b, Operand):
|
|
# print(reg_b)
|
|
if not isinstance(reg_a, Operand):
|
|
reg_a = RegisterOperand(name=reg_a["name"])
|
|
prefixes_gpr = "wx"
|
|
prefixes_vec = "bhsdqvz"
|
|
if reg_a.name == reg_b.name:
|
|
if reg_a.prefix.lower() in prefixes_gpr and reg_b.prefix.lower() in prefixes_gpr:
|
|
return True
|
|
if reg_a.prefix.lower() in prefixes_vec and reg_b.prefix.lower() in prefixes_vec:
|
|
return True
|
|
return False
|
|
|
|
def get_reg_type(self, register):
|
|
"""Get register type"""
|
|
return register.prefix
|