pleroy
1a7c1588f6
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
a8cab3170c
fix #109
2024-10-01 12:00:47 +02:00
JanLJL
c9e38631d1
Flake8 formatting
2024-05-02 17:00:12 +02:00
stefandesouza
78309574ac
added prefetch operand
2024-03-18 22:29:39 +01:00
stefandesouza
4fd59eb0d0
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
5f9de2c41d
Dump now converts classes to dicts
2024-03-05 00:18:45 +01:00
stefandesouza
38781ecc94
Port pressure returned in tuple with Memory Operand
2024-03-04 20:00:43 +01:00
stefandesouza
46004add41
Immediate operand attribute name changes
2024-02-28 13:01:37 +01:00
stefandesouza
dcfe36b850
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
stefandesouza
7ad3438af5
Removed comments from operands
2024-02-24 14:15:25 +01:00
stefandesouza
1fb015b312
Formatting before PR
2024-01-10 13:05:27 +01:00
stefandesouza
226bc8eee0
Added shift and shift_op to Register Operand
2024-01-04 14:34:36 +01:00
stefandesouza
0b3508abf8
Small cleaup commit
2023-12-16 16:00:37 +01:00
stefandesouza
4647615c5c
Merge remote-tracking branch 'origin/master' into InstrucForm
2023-12-16 12:14:36 +01:00
JanLJL
c5ef5f7432
bugfixes for SP reg and ccodes
2023-12-12 18:32:43 +01:00
stefandesouza
339b06bd7f
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
8a6ae8c701
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
cac4a0ebf2
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
cef7f8098d
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
93ae586745
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
2c32ccf37a
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
ebb973493b
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
14a2aa0b52
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
0b2753a78d
Throughput assignment adjustments
2023-09-25 23:20:10 +02:00
stefandesouza
42f96753c1
Black formatting
2023-09-12 12:45:28 +02:00
stefandesouza
7f4f87d192
Changes for operand matching, instruction loading
2023-09-11 18:23:57 +02:00
stefandesouza
36549dd679
Updated list/range register resolver & applied black formatting
2023-08-26 14:51:04 +02:00
stefandesouza
76f3baf74e
Removed all AttrDict() usage in parser. process_operand() now turns single registers into operands
2023-08-21 18:53:56 +02:00
stefandesouza
b06e6424f7
Added eq methods, changed AArch parser tests for class usage
2023-08-21 15:36:40 +02:00
stefandesouza
0a32c77751
Added 2 operand types and made changes for attribute usage
2023-08-20 21:01:44 +02:00
stefandesouza
ecdfc15ac5
InstrucForm class usage in AArch parser
2023-08-20 13:35:11 +02:00
JanLJL
54644ffb09
black-compliant formatting
2023-03-14 18:22:27 +01:00
JanLJL
0b93766bdd
Merge branch 'master' into pr-armcc
2023-03-14 17:50:48 +01:00
JanLJL
d1201ace11
added more dependency analysis for post/pre indexing and condition flags
2023-03-14 17:00:02 +01:00
JanLJL
2884d17971
enabled indexing without shape and lane for vector regs
2023-03-03 14:41:48 +01:00
Décio Luiz Gazzoni Filho
19c47db3ed
Support for flags and conditional ops on AArch64
2023-02-19 22:08:42 -03:00
JanLJL
93c0753db3
formatting
2022-04-07 12:17:08 +02:00
Qingcai Jiang
fa06b9ccac
fix a bug about orr in tsv110
2022-03-20 14:53:34 +08:00
Jan
2be8606e9a
black-conform formatting
2021-12-03 14:38:52 +01:00
Qingcai Jiang
d170ba72dd
fix a bug when the hex_number of address is negative
2021-12-03 15:13:54 +08:00
JanLJL
d418c16f4a
applied flake8 and black rules
2021-08-26 16:58:19 +02:00
JanLJL
090c24ade1
fixed parsing of reg ranges and lists
2021-06-01 00:10:05 +02:00
JanLJL
d59b100fa8
changed immediate type from str to int
2021-05-10 01:12:30 +02:00
Julian Hammer
1f32252f91
improved register range and list support on AArch64
2021-04-23 13:12:18 +02:00
Julian
08440ed5e1
Validation ( #71 )
...
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.
build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.
For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz
The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb
Quite a few changes on OSACA included:
Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
2021-04-15 14:42:37 +02:00
Julian Hammer
6204c90934
migrate code style to Black
2021-03-11 12:02:45 +01:00
Julian Hammer
d7a687909e
passing parsing errors to the outside
2021-03-05 18:07:36 +01:00
JanLJL
74a479fb95
fixed AArch64 parser for register shifts and new instructions for A64FX
2021-02-25 07:43:42 +01:00
JanLJL
23623ca18a
enhancements for lookup and parsing AArch64 instrs
2020-12-07 01:18:32 +01:00
JanLJL
81ce395115
added the possibility of a 5th operand
2020-12-06 18:05:59 +01:00
