JanLJL 8359aa4807 added new instructions/uarchs

2019-11-06 12:30:20 +01:00

..

isa

ibench benchmark file creation

2019-10-04 12:21:19 +02:00

bdw.yml

added missing data ports in DB and nicer CP view for frontend

2019-10-31 19:40:20 +01:00

csx.yml

improved port model scheme

2019-10-31 18:47:50 +01:00

hsw.yml

added new instructions/uarchs

2019-11-06 12:30:20 +01:00

ivb.yml

added new instructions/uarchs

2019-11-06 12:30:20 +01:00

model_importer.py

changed DBs to new port_pressure structure

2019-10-16 10:06:47 +02:00

skx.yml

added new instructions/uarchs

2019-11-06 12:30:20 +01:00

snb.yml

added new instructions/uarchs

2019-11-06 12:30:20 +01:00

tx2.yml

fixed bug in load port utilization

2019-10-29 16:51:58 +01:00

zen1.yml

changed DBs to new port_pressure structure

2019-10-16 10:06:47 +02:00