mirror of
https://github.com/RRZE-HPC/OSACA.git
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70 lines
2.8 KiB
Python
Executable File
70 lines
2.8 KiB
Python
Executable File
#!/usr/bin/env python3
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import sys
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from io import StringIO
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import os
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import unittest
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sys.path.insert(0, '..')
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from osaca import osaca
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class TestOsaca(unittest.TestCase):
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maxDiff = None
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def setUp(self):
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self.curr_dir = '/'.join(os.path.realpath(__file__).split('/')[:-1])
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@unittest.skip("Binary analysis is error prone and currently not working with FSF's objdump")
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def testIACABinary(self):
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assembly = osaca.get_assembly_from_binary(self.curr_dir + '/testfiles/taxCalc-ivb-iaca')
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osa = osaca.OSACA('IVB', assembly)
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result = osa.generate_text_output()
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result = result[result.find('Port Binding in Cycles Per Iteration:'):]
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with open(self.curr_dir + '/test_osaca_iaca.out', encoding='utf-8') as f:
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assertion = f.read()
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self.assertEqual(assertion.replace(' ', ''), result.replace(' ', ''))
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# Test ASM file with IACA marker in two lines
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def testIACAasm1(self):
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with open(self.curr_dir + '/testfiles/taxCalc-ivb-iaca.S') as f:
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osa = osaca.OSACA('IVB', f.read())
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result = osa.generate_text_output()
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result = result[result.find('Port Binding in Cycles Per Iteration:'):]
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with open(self.curr_dir + '/test_osaca_iaca_asm.out', encoding='utf-8') as f:
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assertion = f.read()
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self.assertEqual(assertion.replace(' ', ''), result.replace(' ', ''))
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# Test ASM file with IACA marker in four lines
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def testIACAasm2(self):
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with open(self.curr_dir + '/testfiles/taxCalc-ivb-iaca2.S') as f:
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osa = osaca.OSACA('IVB', f.read())
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result = osa.generate_text_output()
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result = result[result.find('Port Binding in Cycles Per Iteration:'):]
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with open(self.curr_dir + '/test_osaca_iaca_asm.out', encoding='utf-8') as f:
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assertion = f.read()
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self.assertEqual(assertion.replace(' ', ''), result.replace(' ', ''))
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#@unittest.skip("Skip until required instructions are supported.")
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def test_asm_API(self):
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with open(self.curr_dir + '/testfiles/3d-7pt.iaca_marked.s') as f:
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osa = osaca.OSACA('SKL', f.read())
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text_output = osa.create_output()
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print(text_output)
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# Derived from IACA (and manually considering OSACAs equal distribution to ports)
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self.assertEqual(dict(osa.get_port_occupation_cycles()),
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{'0': 4.0,
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'0DV': 0.0,
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'1': 3.5,
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'2': 3.5,
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'3': 3.5,
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'4': 1.0,
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'5': 4.5,
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'6': 3.5,
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'7': 0.0})
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# TODO consider frontend bottleneck -> 6.25 cy
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self.assertEqual(osa.get_total_throughput(),
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4.5)
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