mirror of
https://github.com/RRZE-HPC/OSACA.git
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2249 lines
42 KiB
YAML
2249 lines
42 KiB
YAML
osaca_version: 0.4.6
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micro_architecture: TaiShan v110 # https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
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arch_code: tsv110
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isa: AArch64
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ROB_size: 128 # https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64SchedTSV110.td#L21
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retired_uOps_per_cycle: 4
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scheduler_size: ~ # unknown
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hidden_loads: false
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load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0}
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load_throughput: []
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load_throughput_default: [[1, '67']]
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store_throughput: []
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store_throughput_default: [[1, '67']]
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ports: ['0', '1', '2', '3', '4', '5', '6', '7']
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port_model_scheme: |
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+--------------------------------------------------------------------------------------------+
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| - entries |
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+--------------------------------------------------------------------------------------------+
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0 |ALU 1 |AB 2 |AB 3 |MDU 4 |FSU1 5 |FSU2 6 |LdSt 7 |LdSt
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\/ \/ \/ \/ \/ \/ \/ \/
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+---------+ +---------+ +---------+ +-------------+ +-------+ +------ + +-------+ +-------+
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| INT ALU | | INT ALU | | INT ALU | | Multi-Cycle | | FP | | FP | | LD/ST | | LD/ST |
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+---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+
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+---------+ +---------+ +-------+ +-------+
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instruction_forms:
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- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq]
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operands:
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- class: identifier
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throughput: 0.5
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latency: 0.0
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port_pressure: [[1, '12']]
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# logical instructions: and (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: and
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: and
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: and
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: and
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: ands
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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- name: ands
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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- name: ands
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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- name: ands
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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# logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: orr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: orr
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: orr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: orr
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: eor
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: eor
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: eor
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: eor
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: bic
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: bics (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: bics
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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# shift instructions: lsl (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: lsl
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: lsl
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# shift instructions: lsr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: lsr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: lsr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# shift instructions: asr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: asr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: asr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# arithmetic instructions: add (from AArch64SchedTSV110.td and ibench)
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- name: add
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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- name: add
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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- name: add
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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- name: add
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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latency: 1
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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- name: add
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operands:
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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throughput: 0.5
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latency: 2.0
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port_pressure: [[1, '45']]
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- name: add
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operands:
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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throughput: 0.5
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latency: 2.0
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port_pressure: [[1, '45']]
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- name: add
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operands:
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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throughput: 0.5
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latency: 2.0
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port_pressure: [[1, '45']]
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# arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench)
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- name: adds
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '12']]
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throughput: 0.5
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uops: 1
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- name: adds
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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latency: 1.0
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port_pressure: [[1, '12']]
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throughput: 0.5
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uops: 1
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- name: adds
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1.0
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port_pressure: [[1, '12']]
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throughput: 0.5
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uops: 1
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- name: adds
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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latency: 1.0
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port_pressure: [[1, '12']]
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throughput: 0.5
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uops: 1
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# arithmetic instructions: addp (from AArch64SchedTSV110.td)
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- name: addp
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operands:
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- class: register
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prefix: v
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shape: '*'
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- class: register
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prefix: v
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shape: '*'
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- class: register
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prefix: v
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shape: '*'
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throughput: 0.5
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latency: 5.0
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port_pressure: [[1, '45']]
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# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
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- name: adc
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
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- name: adc
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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latency: 1.0
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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# arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench)
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- name: sub
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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latency: 1.0
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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- name: sub
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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- name: sub
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|
operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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|
latency: 1.0
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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- name: sub
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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latency: 1.0
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port_pressure: [[1, '012']]
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throughput: 0.33333
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uops: 1
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# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
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- name: subs
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1.0
|
|
port_pressure: [[1, '12']]
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throughput: 0.5
|
|
uops: 1
|
|
- name: subs
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1.0
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port_pressure: [[1, '12']]
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throughput: 0.5
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uops: 1
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# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
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- name: mul
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
|
|
- class: register
|
|
prefix: x
|
|
latency: 4.0
|
|
port_pressure: [[1, '3']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: mul
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 7.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 2.5
|
|
uops: 1
|
|
- name: mla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 7.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 2.5
|
|
uops: 1
|
|
- name: mla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 7.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 2.5
|
|
uops: 1
|
|
# arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
|
|
- name: mla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 7.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 2.5
|
|
uops: 1
|
|
- name: mla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 7.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 2.5
|
|
uops: 1
|
|
- name: mla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 7.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 2.5
|
|
uops: 1
|
|
# arithmetic instructions: neg (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: neg
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: neg
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: neg
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: neg
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: neg
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 1.0
|
|
uops: 2
|
|
# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: fadd
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 4.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fadd
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 4.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: fadd
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 5.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.321
|
|
uops: 1
|
|
# arithmetic instructions: fabs (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: fabs
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 2.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fabs
|
|
operands:
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fabs
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 2.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fabs
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
# arithmetic instructions: fsub (latency and throughput from ibench and asmbench, port data from AArch64SchedTSV110.td)
|
|
- name: fsub
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 5.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fsub
|
|
operands:
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
latency: 4.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fsub
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 4.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: fsub
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 5.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
# arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: fmul
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 5.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: fmul
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 5.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: fmul
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 5.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
# arithmetic instructions: fdiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
|
|
- name: fdiv
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 6.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 6.0
|
|
uops: 1
|
|
- name: fdiv
|
|
operands:
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
latency: 6.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 6.0
|
|
uops: 1
|
|
- name: fdiv
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 16.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 12..0
|
|
uops: 1
|
|
- name: fdiv
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 16.0
|
|
port_pressure: [[1, '4']]
|
|
throughput: 12.0
|
|
uops: 1
|
|
# arithmetic instructions: fmla (latency and throughput from ibench, uops and port data missed)
|
|
- name: fmla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 5.0
|
|
port_pressure: ~
|
|
throughput: 0.5
|
|
uops: ~
|
|
- name: fmla
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 7.0
|
|
port_pressure: ~
|
|
throughput: 1.0
|
|
uops: ~
|
|
# arithmetic instructions: fsqrt (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
|
|
- name: fsqrt
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 9.0
|
|
port_pressure: [[1, '5']]
|
|
throughput: 9.0
|
|
uops: 1
|
|
- name: fsqrt
|
|
operands:
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
- class: register
|
|
prefix: s
|
|
latency: 9.0
|
|
port_pressure: [[1, '5']]
|
|
throughput: 9.0
|
|
uops: 1
|
|
- name: fsqrt
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 22.0
|
|
port_pressure: [[1, '5']]
|
|
throughput: 18.0
|
|
uops: 1
|
|
- name: fsqrt
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 22.0
|
|
port_pressure: [[1, '5']]
|
|
throughput: 18.0
|
|
uops: 1
|
|
# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: frecpe
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 3.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: frecpe
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 3.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
# arithmetic instructions: fcmp (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: fcmp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: immediate
|
|
imd: float
|
|
latency: 3.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: fcmp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 3.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion)
|
|
- name: mov
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: register
|
|
prefix: w
|
|
latency: 0.0
|
|
port_pressure: []
|
|
throughput: 0.0
|
|
uops: 0
|
|
- name: mov
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
latency: 0.0
|
|
port_pressure: []
|
|
throughput: 0.0
|
|
uops: 0
|
|
- name: mov
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
latency: 0.0
|
|
port_pressure: []
|
|
throughput: 0.0
|
|
uops: 0
|
|
- name: mov
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
latency: 0.0
|
|
port_pressure: []
|
|
throughput: 0.0
|
|
uops: 0
|
|
- name: mov
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: '*'
|
|
- class: register
|
|
prefix: v
|
|
shape: '*'
|
|
latency: 0.0
|
|
port_pressure: []
|
|
throughput: 0.0
|
|
uops: 0
|
|
# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
|
|
- name: dup
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: x
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.667
|
|
uops: 2
|
|
- name: dup
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: w
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.667
|
|
uops: 2
|
|
# miscellaneous instructions: cmn (throughput from ibench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: cmn
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: cmn
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: register
|
|
prefix: w
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: cmn
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: immediate
|
|
imd: int
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: cmn
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: immediate
|
|
imd: int
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: cmp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: cmp
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: register
|
|
prefix: w
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: cmp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: immediate
|
|
imd: int
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: cmp
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: immediate
|
|
imd: int
|
|
latency: 1.0
|
|
port_pressure: [[1, '12']]
|
|
throughput: 0.5
|
|
uops: 1
|
|
# miscellaneous instructions: dup (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: dup
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: x
|
|
throughput: 0.667
|
|
latency: 2.0
|
|
port_pressure: [[1, '5']]
|
|
uops: 1
|
|
- name: dup
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: w
|
|
throughput: 0.667
|
|
latency: 2.0
|
|
port_pressure: [[1, '5']]
|
|
uops: 1
|
|
# miscellaneous instructions: extr (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: extr
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: immediate
|
|
imd: int
|
|
throughput: 0.333
|
|
latency: 1.0
|
|
port_pressure: [[1, '012']]
|
|
uops: 1
|
|
# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: zip1
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: zip1
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: zip1
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
# miscellaneous instructions: zip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: zip2
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: zip2
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: zip2
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
# miscellaneous instructions: uzip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: uzip1
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: uzip1
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: uzip1
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
# miscellaneous instructions: uzip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
|
- name: uzip2
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
- class: register
|
|
prefix: v
|
|
shape: b
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: uzip2
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
- class: register
|
|
prefix: v
|
|
shape: h
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: uzip2
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 2.0
|
|
port_pressure: [[1, '4'], [1, '5']]
|
|
throughput: 0.5
|
|
uops: 2
|
|
# miscellaneous instructions: scvtf (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions)
|
|
- name: scvtf
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
- class: register
|
|
prefix: v
|
|
shape: d
|
|
latency: 3.0
|
|
port_pressure: [[1, '45']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: scvtf
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
- class: register
|
|
prefix: v
|
|
shape: s
|
|
latency: 3.0
|
|
port_pressure: [[2, '45']]
|
|
throughput: 2.0
|
|
uops: 1
|
|
# miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion)
|
|
- name: fmov
|
|
operands:
|
|
- class: register
|
|
prefix: s
|
|
- class: immediate
|
|
imd: int
|
|
latency: 0.0
|
|
port_pressure: []
|
|
throughput: 0.0
|
|
uops: 0
|
|
# memory instructions: ldur (data from AArch64SchedTSV110.td)
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 4.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 4.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 4.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldr
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 5.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
# memory instructions: str (data from AArch64SchedTSV110.td)
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: str
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 0.5
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
# memory instructions: ldur (data from AArch64SchedTSV110.td)
|
|
- name: ldur
|
|
operands:
|
|
- class: register
|
|
prefix: w
|
|
- class: memory
|
|
base: x
|
|
offset: imd
|
|
index: '*'
|
|
scale: '*'
|
|
post-indexed: false
|
|
pre-indexed: false
|
|
throughput: 0.5
|
|
latency: 4.0
|
|
port_pressure: [[1, '67']]
|
|
# memory instructions: stur (data from AArch64SchedTSV110.td)
|
|
- name: stur
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
- name: stur
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 0.5
|
|
latency: 1.0
|
|
port_pressure: [[1, '67']]
|
|
uops: 1
|
|
# memory instructions: ldp (data from AArch64SchedTSV110.td)
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 8.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 8.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
- name: ldp
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 1.0
|
|
latency: 9.0
|
|
port_pressure: [[2, '67'], [2, '012']]
|
|
uops: 4
|
|
# memory instructions: stp (data from AArch64SchedTSV110.td)
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[2, '67']]
|
|
uops: 2
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[1, '67'], [1, '012']]
|
|
uops: 2
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[2, '67']]
|
|
uops: 2
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[2, '67'], [1, '012']]
|
|
uops: 3
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: d
|
|
- class: register
|
|
prefix: d
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[2, '67'], [1, '012']]
|
|
uops: 3
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[2, '67']]
|
|
uops: 2
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: true
|
|
post-indexed: false
|
|
throughput: 1.0
|
|
latency: 3.0
|
|
port_pressure: [[2, '67'], [1, '012']]
|
|
uops: 3
|
|
- name: stp
|
|
operands:
|
|
- class: register
|
|
prefix: q
|
|
- class: register
|
|
prefix: q
|
|
- class: memory
|
|
base: x
|
|
offset: '*'
|
|
index: '*'
|
|
scale: '*'
|
|
pre-indexed: false
|
|
post-indexed: true
|
|
throughput: 1.0
|
|
latency: 2.0
|
|
port_pressure: [[2, '67'], [1, '012']]
|
|
uops: 3
|