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add some instructions for tsv110

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Qingcai Jiang
2021-12-18 15:44:07 +08:00
parent 4e10491fcb
commit a738d82533
1 changed files with 183 additions and 8 deletions
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191
osaca/data/tsv110.yml
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@@ -301,6 +301,31 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
# shift instructions: asr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: asr
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: asr
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
# arithmetic instructions: add (from AArch64SchedTSV110.td and ibench)
- name: add
operands:
@@ -440,6 +465,21 @@ instruction_forms:
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
# arithmetic instructions: addp (from AArch64SchedTSV110.td)
- name: addp
operands:
- class: register
prefix: v
shape: '*'
- class: register
prefix: v
shape: '*'
- class: register
prefix: v
shape: '*'
throughput: 0.5
latency: 5.0
port_pressure: [[1, '45']]
# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
- name: adc
operands:
@@ -744,8 +784,53 @@ instruction_forms:
port_pressure: [[1, '45']]
throughput: 1.321
uops: 1
# arithmetic instructions: fabs (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
- name: fabs
operands:
- class: register
prefix: d
- class: register
prefix: d
latency: 2.0
port_pressure: [[1, '45']]
throughput: 0.5
uops: 1
- name: fabs
operands:
- class: register
prefix: s
- class: register
prefix: s
latency: 2.0
port_pressure: [[1, '45']]
throughput: 0.5
uops: 1
- name: fabs
operands:
- class: register
prefix: v
shape: d
- class: register
prefix: v
shape: d
latency: 2.0
port_pressure: [[1, '45']]
throughput: 0.5
uops: 1
- name: fabs
operands:
- class: register
prefix: v
shape: s
- class: register
prefix: v
shape: s
latency: 2.0
port_pressure: [[1, '45']]
throughput: 0.5
uops: 1
# arithmetic instructions: fsub (latency and throughput from ibench and asmbench, port data from AArch64SchedTSV110.td)
- name: fadd
- name: fsub
operands:
- class: register
prefix: d
@@ -757,7 +842,7 @@ instruction_forms:
port_pressure: [[1, '45']]
throughput: 0.5
uops: 1
- name: fadd
- name: fsub
operands:
- class: register
prefix: s
@@ -1008,6 +1093,27 @@ instruction_forms:
port_pressure: [[1, '45']]
throughput: 1.0
uops: 1
# arithmetic instructions: fcmp (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
- name: fcmp
operands:
- class: register
prefix: d
- class: immediate
imd: float
latency: 3.0
port_pressure: [[1, '45']]
throughput: 1.0
uops: 1
- name: fcmp
operands:
- class: register
prefix: d
- class: register
prefix: d
latency: 3.0
port_pressure: [[1, '45']]
throughput: 1.0
uops: 1
# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion)
- name: mov
operands:
@@ -1064,15 +1170,67 @@ instruction_forms:
# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
- name: dup
operands:
- class: register
prefix: d
- class: register
prefix: v
shape: d
- class: register
prefix: x
latency: 2.0
port_pressure: [[1, '4'], [1, '5']]
throughput: 0.667
uops: 2
- name: dup
operands:
- class: register
prefix: v
shape: s
- class: register
prefix: w
latency: 2.0
port_pressure: [[1, '4'], [1, '5']]
throughput: 0.667
uops: 2
# miscellaneous instructions: cmn (throughput from ibench, latency and port data from AArch64SchedTSV110.td)
- name: cmn
operands:
- class: register
prefix: x
- class: register
prefix: x
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: cmn
operands:
- class: register
prefix: w
- class: register
prefix: w
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: cmn
operands:
- class: register
prefix: x
- class: immediate
imd: int
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: cmn
operands:
- class: register
prefix: w
- class: immediate
imd: int
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td)
- name: cmp
operands:
@@ -1081,7 +1239,7 @@ instruction_forms:
- class: register
prefix: x
latency: 1.0
port_pressure: [1, '12']
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: cmp
@@ -1091,7 +1249,7 @@ instruction_forms:
- class: register
prefix: w
latency: 1.0
port_pressure: [1, '12']
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: cmp
@@ -1101,7 +1259,7 @@ instruction_forms:
- class: immediate
imd: int
latency: 1.0
port_pressure: [1, '12']
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: cmp
@@ -1111,7 +1269,7 @@ instruction_forms:
- class: immediate
imd: int
latency: 1.0
port_pressure: [1, '12']
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
# miscellaneous instructions: dup (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
@@ -1125,6 +1283,7 @@ instruction_forms:
throughput: 0.667
latency: 2.0
port_pressure: [[1, '5']]
uops: 1
- name: dup
operands:
- class: register
@@ -1135,6 +1294,22 @@ instruction_forms:
throughput: 0.667
latency: 2.0
port_pressure: [[1, '5']]
uops: 1
# miscellaneous instructions: extr (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: extr
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: zip1
operands: