mirror of
https://github.com/RRZE-HPC/OSACA.git
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808 lines
34 KiB
Python
808 lines
34 KiB
Python
#!/usr/bin/env python3
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import pyparsing as pp
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import unicodedata
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from osaca.parser import ParserX86
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from osaca.parser.directive import DirectiveOperand
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from osaca.parser.identifier import IdentifierOperand
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from osaca.parser.immediate import ImmediateOperand
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from osaca.parser.instruction_form import InstructionForm
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from osaca.parser.label import LabelOperand
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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# We assume any non-ASCII characters except control characters and line terminators can be part of
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# identifiers; this is based on the assumption that no assembler uses non-ASCII white space and
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# syntax characters.
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# This approach is described at the end of https://www.unicode.org/reports/tr55/#Whitespace-Syntax.
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# It is appropriate for tools, such as this one, which process source code but do not fully validate
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# it (in this case, that’s the job of the assembler).
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NON_ASCII_PRINTABLE_CHARACTERS = "".join(
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chr(cp)
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for cp in range(0x80, 0x10FFFF + 1)
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if unicodedata.category(chr(cp)) not in ("Cc", "Zl", "Zp", "Cs", "Cn")
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)
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# References:
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# ASM386 Assembly Language Reference, document number 469165-003, https://mirror.math.princeton.edu/pub/oldlinux/Linux.old/Ref-docs/asm-ref.pdf.
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# Microsoft Macro Assembler BNF Grammar, https://learn.microsoft.com/en-us/cpp/assembler/masm/masm-bnf-grammar?view=msvc-170.
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# Intel Architecture Code Analyzer User's Guide, https://www.intel.com/content/dam/develop/external/us/en/documents/intel-architecture-code-analyzer-3-0-users-guide-157552.pdf.
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class ParserX86Intel(ParserX86):
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_instance = None
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# Singleton pattern, as this is created very many times.
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def __new__(cls):
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if cls._instance is None:
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cls._instance = super(ParserX86Intel, cls).__new__(cls)
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return cls._instance
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def __init__(self):
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super().__init__()
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self._equ = {}
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# The IACA manual says: "For For Microsoft* Visual C++ compiler, 64-bit version, use
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# IACA_VC64_START and IACA_VC64_END, instead" (of IACA_START and IACA_END).
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# TODO: Inconveniently, the code generated with optimization disabled (/Od) has two
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# instructions. We should support both patterns, but then who runs OSACA with /Od?
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def start_marker(self):
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return [
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InstructionForm(
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mnemonic="mov",
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operands=[
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MemoryOperand(
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base=RegisterOperand(name="GS"), offset=ImmediateOperand(value=111)
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),
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ImmediateOperand(value=111),
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],
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),
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]
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def end_marker(self):
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return [
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InstructionForm(
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mnemonic="mov",
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operands=[
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MemoryOperand(
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base=RegisterOperand(name="GS"), offset=ImmediateOperand(value=222)
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),
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ImmediateOperand(value=222),
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],
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),
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]
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def normalize_instruction_form(self, instruction_form, isa_model, arch_model):
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"""
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If the model indicates that this instruction has a single destination that is the last
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operand, move the first operand to the last position. This effectively converts the Intel
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syntax to the AT&T one.
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"""
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if instruction_form.normalized:
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return
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instruction_form.normalized = True
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mnemonic = instruction_form.mnemonic
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if not mnemonic:
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return
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# The model may only contain the VEX-encoded instruction and we may have the non-VEX-encoded
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# one, or vice-versa. Note that this doesn't work when the arguments differ between VEX-
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# encoded and non-VEX-encoded, e.g., for psubq.
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if not arch_model.get_instruction(mnemonic, len(instruction_form.operands)):
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if mnemonic[0] == "v":
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unvexed_mnemonic = mnemonic[1:]
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if arch_model.get_instruction(unvexed_mnemonic, len(instruction_form.operands)):
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mnemonic = unvexed_mnemonic
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else:
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vexed_mnemonic = "v" + mnemonic
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if arch_model.get_instruction(vexed_mnemonic, len(instruction_form.operands)):
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mnemonic = vexed_mnemonic
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instruction_form.mnemonic = mnemonic
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# We cannot pass the operands because they may not match before the reordering. We just
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# pass the arity instead. Also, this must use the ISA model, because that's where the
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# source/destination information is found.
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model = isa_model.get_instruction(mnemonic, len(instruction_form.operands))
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has_single_destination_at_end = False
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has_destination = False
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if model:
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for o in model.operands:
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if o.source:
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if has_destination:
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has_single_destination_at_end = False
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if o.destination:
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if has_destination:
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has_single_destination_at_end = False
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else:
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has_destination = True
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has_single_destination_at_end = True
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else:
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# if there is only one operand, assume it is a source operand
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has_single_destination_at_end = len(instruction_form.operands) > 1
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if has_single_destination_at_end:
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# It is important to reverse the operands, we cannot just move the first one last. This
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# makes a difference for instructions with 3 operands or more, such as roundsd: the
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# model files expect the rounding mode (an immediate) first but the Intel syntax has it
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# last.
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instruction_form.operands.reverse()
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# A hack to help with comparison instruction: if the instruction is in the model, and has
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# exactly two sources, swap its operands.
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if (
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model
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and not has_destination
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and len(instruction_form.operands) == 2
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and not isa_model.get_instruction(mnemonic, instruction_form.operands)
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and not arch_model.get_instruction(mnemonic, instruction_form.operands)
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):
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instruction_form.operands.reverse()
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# If the instruction has a well-known data type, append a suffix.
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data_type_to_suffix = {"DWORD": "d", "QWORD": "q"}
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for o in instruction_form.operands:
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if isinstance(o, MemoryOperand) and o.data_type:
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suffix = data_type_to_suffix.get(o.data_type, None)
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if suffix:
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suffixed_mnemonic = mnemonic + suffix
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if isa_model.get_instruction(
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suffixed_mnemonic, len(instruction_form.operands)
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) or arch_model.get_instruction(
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suffixed_mnemonic, len(instruction_form.operands)
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):
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instruction_form.mnemonic = suffixed_mnemonic
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break
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def construct_parser(self):
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"""Create parser for x86 Intel ISA."""
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# Numeric literal.
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binary_number = pp.Combine(pp.Word("01") + pp.CaselessLiteral("B"))
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octal_number = pp.Combine(pp.Word("01234567") + pp.CaselessLiteral("O"))
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decimal_number = pp.Combine(pp.Optional(pp.Literal("-")) + pp.Word(pp.nums))
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hex_number = pp.Combine(pp.Word(pp.hexnums) + pp.CaselessLiteral("H"))
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float_number = pp.Combine(
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pp.Optional(pp.Literal("-")) + pp.Word(pp.nums) + pp.Word(".", pp.nums)
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).setResultsName("value")
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integer_number = (
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binary_number ^ octal_number ^ decimal_number ^ hex_number
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).setResultsName("value")
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# Comment.
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self.comment = pp.Word(";#", exact=1) + pp.Group(
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pp.ZeroOrMore(pp.Word(pp.printables + NON_ASCII_PRINTABLE_CHARACTERS))
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).setResultsName(self.comment_id)
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# Types.
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data_type = (
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pp.CaselessKeyword("BYTE")
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| pp.CaselessKeyword("DWORD")
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| pp.CaselessKeyword("FWORD")
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| pp.CaselessKeyword("MMWORD")
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| pp.CaselessKeyword("OWORD")
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| pp.CaselessKeyword("QWORD")
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| pp.CaselessKeyword("REAL10")
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| pp.CaselessKeyword("REAL4")
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| pp.CaselessKeyword("REAL8")
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| pp.CaselessKeyword("SBYTE")
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| pp.CaselessKeyword("SDWORD")
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| pp.CaselessKeyword("SQWORD")
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| pp.CaselessKeyword("SWORD")
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| pp.CaselessKeyword("TBYTE")
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| pp.CaselessKeyword("WORD")
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| pp.CaselessKeyword("XMMWORD")
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| pp.CaselessKeyword("YMMWORD")
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).setResultsName("data_type")
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# Identifier. Note that $ is not mentioned in the ASM386 Assembly Language Reference,
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# but it is mentioned in the MASM syntax. < and > apparently show up in C++ mangled names.
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# ICC allows ".", at least in labels.
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first = pp.Word(pp.alphas + NON_ASCII_PRINTABLE_CHARACTERS + ".$?@_<>", exact=1)
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rest = pp.Word(pp.alphanums + NON_ASCII_PRINTABLE_CHARACTERS + ".$?@_<>")
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identifier = pp.Group(
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pp.Combine(first + pp.Optional(rest)).setResultsName("name")
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).setResultsName("identifier")
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# Register.
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# This follows the MASM grammar.
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special_register = (
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pp.CaselessKeyword("CR0")
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| pp.CaselessKeyword("CR2")
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| pp.CaselessKeyword("CR3")
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| pp.CaselessKeyword("DR0")
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| pp.CaselessKeyword("DR1")
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| pp.CaselessKeyword("DR2")
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| pp.CaselessKeyword("DR3")
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| pp.CaselessKeyword("DR6")
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| pp.CaselessKeyword("DR7")
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| pp.CaselessKeyword("TR3")
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| pp.CaselessKeyword("TR4")
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| pp.CaselessKeyword("TR5")
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| pp.CaselessKeyword("TR6")
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| pp.CaselessKeyword("TR7")
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).setResultsName("name")
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gp_register = (
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pp.CaselessKeyword("AX")
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| pp.CaselessKeyword("EAX")
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| pp.CaselessKeyword("CX")
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| pp.CaselessKeyword("ECX")
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| pp.CaselessKeyword("DX")
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| pp.CaselessKeyword("EDX")
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| pp.CaselessKeyword("BX")
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| pp.CaselessKeyword("EBX")
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| pp.CaselessKeyword("DI")
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| pp.CaselessKeyword("EDI")
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| pp.CaselessKeyword("SI")
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| pp.CaselessKeyword("ESI")
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| pp.CaselessKeyword("BP")
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| pp.CaselessKeyword("EBP")
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| pp.CaselessKeyword("SP")
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| pp.CaselessKeyword("ESP")
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| pp.CaselessKeyword("R8W")
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| pp.CaselessKeyword("R8D")
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| pp.CaselessKeyword("R9W")
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| pp.CaselessKeyword("R9D")
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| pp.CaselessKeyword("R12D")
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| pp.CaselessKeyword("R13W")
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| pp.CaselessKeyword("R13D")
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| pp.CaselessKeyword("R14W")
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| pp.CaselessKeyword("R14D")
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).setResultsName("name")
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byte_register = (
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pp.CaselessKeyword("AL")
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| pp.CaselessKeyword("AH")
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| pp.CaselessKeyword("CL")
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| pp.CaselessKeyword("CH")
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| pp.CaselessKeyword("DL")
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| pp.CaselessKeyword("DH")
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| pp.CaselessKeyword("BL")
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| pp.CaselessKeyword("BH")
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| pp.CaselessKeyword("R8B")
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| pp.CaselessKeyword("R9B")
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| pp.CaselessKeyword("R10B")
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| pp.CaselessKeyword("R11B")
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| pp.CaselessKeyword("R12B")
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| pp.CaselessKeyword("R13B")
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).setResultsName("name")
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qword_register = (
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pp.CaselessKeyword("RAX")
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| pp.CaselessKeyword("RCX")
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| pp.CaselessKeyword("RDX")
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| pp.CaselessKeyword("RBX")
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| pp.CaselessKeyword("RSP")
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| pp.CaselessKeyword("RBP")
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| pp.CaselessKeyword("RSI")
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| pp.CaselessKeyword("RDI")
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| pp.CaselessKeyword("R8")
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| pp.CaselessKeyword("R9")
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| pp.CaselessKeyword("R10")
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| pp.CaselessKeyword("R11")
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| pp.CaselessKeyword("R12")
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| pp.CaselessKeyword("R13")
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| pp.CaselessKeyword("R14")
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| pp.CaselessKeyword("R15")
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).setResultsName("name")
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fpu_register = pp.Combine(
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pp.CaselessKeyword("ST")
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+ pp.Optional(pp.Literal("(") + pp.Word("01234567") + pp.Literal(")"))
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).setResultsName("name")
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xmm_register = pp.Combine(pp.CaselessLiteral("XMM") + pp.Word(pp.nums)) | pp.Combine(
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pp.CaselessLiteral("XMM1") + pp.Word("012345")
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)
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simd_register = (
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pp.Combine(pp.CaselessLiteral("MM") + pp.Word("01234567"))
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| xmm_register
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| pp.Combine(pp.CaselessLiteral("YMM") + pp.Word(pp.nums))
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| pp.Combine(pp.CaselessLiteral("YMM1") + pp.Word("012345"))
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).setResultsName("name")
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segment_register = (
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pp.CaselessKeyword("CS")
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| pp.CaselessKeyword("DS")
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| pp.CaselessKeyword("ES")
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| pp.CaselessKeyword("FS")
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| pp.CaselessKeyword("GS")
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| pp.CaselessKeyword("SS")
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).setResultsName("name")
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self.register = pp.Group(
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special_register
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| gp_register
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| byte_register
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| qword_register
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| fpu_register
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| simd_register
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| segment_register
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| pp.CaselessKeyword("RIP")
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).setResultsName(self.register_id)
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# Register expressions.
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base_register = self.register
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index_register = self.register
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scale = pp.Word("1248", exact=1)
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base = base_register.setResultsName("base")
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displacement = pp.Group(
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pp.Group(integer_number ^ identifier).setResultsName(self.immediate_id)
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).setResultsName("displacement")
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short_indexed = index_register.setResultsName("index")
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long_indexed = (
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index_register.setResultsName("index")
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+ pp.Literal("*")
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+ scale.setResultsName("scale")
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)
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indexed = pp.Group(short_indexed ^ long_indexed).setResultsName("indexed")
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operator = pp.Word("+-", exact=1)
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operator_index = pp.Word("+-", exact=1).setResultsName("operator_idx")
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operator_displacement = pp.Word("+-", exact=1).setResultsName("operator_disp")
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# Syntax:
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# `base` always preceedes `indexed`.
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# `short_indexed` is only allowed if it follows `base`, not alone.
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# `displacement` can go anywhere.
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# It's easier to list all the alternatives than to represent these rules using complicated
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# `Optional` and what not.
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register_expression = pp.Group(
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pp.Literal("[")
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+ (
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base
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^ (base + operator_displacement + displacement)
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^ (base + operator_displacement + displacement + operator_index + indexed)
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^ (base + operator_index + indexed)
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^ (base + operator_index + indexed + operator_displacement + displacement)
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^ (displacement + operator + base)
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^ (displacement + operator + base + operator_index + indexed)
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^ (
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displacement
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+ operator_index
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+ pp.Group(long_indexed).setResultsName("indexed")
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)
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^ pp.Group(long_indexed).setResultsName("indexed")
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^ (
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pp.Group(long_indexed).setResultsName("indexed")
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+ operator_displacement
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+ displacement
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)
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)
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+ pp.Literal("]")
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).setResultsName("register_expression")
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# Immediate.
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immediate = pp.Group(integer_number | float_number | identifier).setResultsName(
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self.immediate_id
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)
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# Expressions.
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# The ASM86 manual has weird expressions on page 130 (displacement outside of the register
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# expression, multiple register expressions). Let's ignore those for now, but see
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# https://stackoverflow.com/questions/71540754/why-sometimes-use-offset-flatlabel-and-sometimes-not.
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address_expression = pp.Group(
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self.register.setResultsName("segment") + pp.Literal(":") + immediate
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^ immediate + register_expression
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^ register_expression
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^ identifier + pp.Optional(operator + immediate)
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).setResultsName("address_expression")
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offset_expression = pp.Group(
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pp.CaselessKeyword("OFFSET")
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+ pp.Group(
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pp.CaselessKeyword("GROUP")
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| pp.CaselessKeyword("SEGMENT")
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| pp.CaselessKeyword("FLAT")
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)
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# The MASM grammar has the ":" immediately after "OFFSET", but that's not what MSVC
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# outputs.
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+ pp.Literal(":")
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+ identifier.setResultsName("identifier")
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+ pp.Optional(pp.Literal("+") + immediate.setResultsName("displacement"))
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).setResultsName("offset_expression")
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ptr_expression = pp.Group(
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data_type + pp.CaselessKeyword("PTR") + address_expression
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).setResultsName("ptr_expression")
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short_expression = pp.Group(pp.CaselessKeyword("SHORT") + identifier).setResultsName(
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"short_expression"
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)
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# Instructions.
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mnemonic = pp.Word(pp.alphas, pp.alphanums).setResultsName("mnemonic")
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operand = pp.Group(
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self.register
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| pp.Group(
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offset_expression | ptr_expression | short_expression | address_expression
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).setResultsName(self.memory_id)
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| immediate
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)
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self.instruction_parser = (
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mnemonic
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+ pp.Optional(operand.setResultsName("operand1"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand.setResultsName("operand2"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand.setResultsName("operand3"))
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+ pp.Optional(pp.Suppress(pp.Literal(",")))
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+ pp.Optional(operand.setResultsName("operand4"))
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+ pp.Optional(self.comment)
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)
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# Label.
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self.label = pp.Group(
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identifier.setResultsName("name")
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+ pp.Literal(":")
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+ pp.Optional(self.instruction_parser)
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+ pp.Optional(self.comment)
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).setResultsName(self.label_id)
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# Directives.
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# The identifiers at the beginnig of a directive cannot start with a "." otherwise we end up
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# with ambiguities.
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directive_first = pp.Word(pp.alphas + NON_ASCII_PRINTABLE_CHARACTERS + "$?@_<>", exact=1)
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directive_rest = pp.Word(pp.alphanums + NON_ASCII_PRINTABLE_CHARACTERS + ".$?@_<>")
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directive_identifier = pp.Group(
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pp.Combine(directive_first + pp.Optional(directive_rest)).setResultsName("name")
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).setResultsName("identifier")
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# Parameter can be any quoted string or sequence of characters besides ';' (for comments)
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# or ',' (parameter delimiter). See ASM386 p. 38.
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directive_parameter = (
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pp.quotedString
|
||
^ (
|
||
pp.Word(pp.printables + NON_ASCII_PRINTABLE_CHARACTERS, excludeChars=",;")
|
||
+ pp.Optional(pp.Suppress(pp.Literal(",")))
|
||
)
|
||
^ pp.Suppress(pp.Literal(","))
|
||
)
|
||
# The directives that don't start with a "." are ambiguous with instructions, so we list
|
||
# them explicitly.
|
||
# TODO: The directives that are types introduce a nasty ambiguity with instructions. Skip
|
||
# them for now, apparently the MSVC output uses the short D? directives.
|
||
directive_keywords = (
|
||
pp.CaselessKeyword("ALIAS")
|
||
| pp.CaselessKeyword("ALIGN")
|
||
| pp.CaselessKeyword("ASSUME")
|
||
# | pp.CaselessKeyword("BYTE")
|
||
| pp.CaselessKeyword("CATSTR")
|
||
| pp.CaselessKeyword("COMM")
|
||
| pp.CaselessKeyword("COMMENT")
|
||
| pp.CaselessKeyword("DB")
|
||
| pp.CaselessKeyword("DD")
|
||
| pp.CaselessKeyword("DF")
|
||
| pp.CaselessKeyword("DQ")
|
||
| pp.CaselessKeyword("DT")
|
||
| pp.CaselessKeyword("DW")
|
||
# | pp.CaselessKeyword("DWORD")
|
||
| pp.CaselessKeyword("ECHO")
|
||
| pp.CaselessKeyword("END")
|
||
| pp.CaselessKeyword("ENDP")
|
||
| pp.CaselessKeyword("ENDS")
|
||
| pp.CaselessKeyword("EQU")
|
||
| pp.CaselessKeyword("EVEN")
|
||
| pp.CaselessKeyword("EXTRN")
|
||
| pp.CaselessKeyword("EXTERNDEF")
|
||
# | pp.CaselessKeyword("FWORD")
|
||
| pp.CaselessKeyword("GROUP")
|
||
| pp.CaselessKeyword("INCLUDE")
|
||
| pp.CaselessKeyword("INCLUDELIB")
|
||
| pp.CaselessKeyword("INSTR")
|
||
| pp.CaselessKeyword("INVOKE")
|
||
| pp.CaselessKeyword("LABEL")
|
||
# | pp.CaselessKeyword("MMWORD")
|
||
| pp.CaselessKeyword("OPTION")
|
||
| pp.CaselessKeyword("ORG")
|
||
| pp.CaselessKeyword("PAGE")
|
||
| pp.CaselessKeyword("POPCONTEXT")
|
||
| pp.CaselessKeyword("PROC")
|
||
| pp.CaselessKeyword("PROTO")
|
||
| pp.CaselessKeyword("PUBLIC")
|
||
| pp.CaselessKeyword("PUSHCONTEXT")
|
||
# | pp.CaselessKeyword("QWORD")
|
||
# | pp.CaselessKeyword("REAL10")
|
||
# | pp.CaselessKeyword("REAL4")
|
||
# | pp.CaselessKeyword("REAL8")
|
||
| pp.CaselessKeyword("RECORD")
|
||
# | pp.CaselessKeyword("SBYTE")
|
||
# | pp.CaselessKeyword("SDWORD")
|
||
| pp.CaselessKeyword("SEGMENT")
|
||
| pp.CaselessKeyword("SIZESTR")
|
||
| pp.CaselessKeyword("STRUCT")
|
||
| pp.CaselessKeyword("SUBSTR")
|
||
| pp.CaselessKeyword("SUBTITLE")
|
||
# | pp.CaselessKeyword("SWORD")
|
||
# | pp.CaselessKeyword("TBYTE")
|
||
| pp.CaselessKeyword("TEXTEQU")
|
||
| pp.CaselessKeyword("TITLE")
|
||
| pp.CaselessKeyword("TYPEDEF")
|
||
| pp.CaselessKeyword("UNION")
|
||
# | pp.CaselessKeyword("WORD")
|
||
# | pp.CaselessKeyword("XMMWORD")
|
||
# | pp.CaselessKeyword("YMMWORD")
|
||
)
|
||
self.directive = pp.Group(
|
||
pp.Optional(~directive_keywords + directive_identifier)
|
||
+ (
|
||
pp.Combine(pp.Literal(".") + pp.Word(pp.alphanums + "_"))
|
||
| pp.Literal("=")
|
||
| directive_keywords
|
||
).setResultsName("name")
|
||
+ pp.ZeroOrMore(directive_parameter).setResultsName("parameters")
|
||
+ pp.Optional(self.comment)
|
||
).setResultsName(self.directive_id)
|
||
|
||
def parse_line(self, line, line_number=None):
|
||
"""
|
||
Parse line and return instruction form.
|
||
|
||
:param str line: line of assembly code
|
||
:param line_number: default None, identifier of instruction form
|
||
:type line_number: int, optional
|
||
:return: ``dict`` -- parsed asm line (comment, label, directive or instruction form)
|
||
"""
|
||
instruction_form = InstructionForm(line=line, line_number=line_number)
|
||
result = None
|
||
|
||
# 1. Parse comment.
|
||
try:
|
||
result = self.process_operand(self.comment.parseString(line, parseAll=True))
|
||
instruction_form.comment = " ".join(result[self.comment_id])
|
||
except pp.ParseException:
|
||
pass
|
||
|
||
# 2. Parse label.
|
||
if not result:
|
||
try:
|
||
# Returns tuple with label operand and comment, if any.
|
||
result = self.process_operand(self.label.parseString(line, parseAll=True))
|
||
instruction_form.label = result[0].name
|
||
if result[1]:
|
||
instruction_form.comment = " ".join(result[1])
|
||
except pp.ParseException:
|
||
pass
|
||
|
||
# 3. Parse directive.
|
||
if not result:
|
||
try:
|
||
# Returns tuple with directive operand and comment, if any.
|
||
result = self.process_operand(self.directive.parseString(line, parseAll=True))
|
||
instruction_form.directive = result[0]
|
||
if result[1]:
|
||
instruction_form.comment = " ".join(result[1])
|
||
except pp.ParseException:
|
||
pass
|
||
|
||
# 4. Parse instruction.
|
||
if not result:
|
||
try:
|
||
result = self.parse_instruction(line)
|
||
except pp.ParseException as e:
|
||
raise ValueError(
|
||
"Could not parse instruction on line {}: {!r}".format(line_number, line)
|
||
) from e
|
||
instruction_form.mnemonic = result.mnemonic
|
||
instruction_form.operands = result.operands
|
||
instruction_form.comment = result.comment
|
||
return instruction_form
|
||
|
||
def make_instruction(self, parse_result):
|
||
"""
|
||
Parse instruction in asm line.
|
||
|
||
:param parse_result: tuple resulting from calling `parseString` on the `instruction_parser`.
|
||
:returns: `dict` -- parsed instruction form
|
||
"""
|
||
operands = []
|
||
# Add operands to list
|
||
# Check first operand
|
||
if "operand1" in parse_result:
|
||
operands.append(self.process_operand(parse_result.operand1))
|
||
# Check second operand
|
||
if "operand2" in parse_result:
|
||
operands.append(self.process_operand(parse_result.operand2))
|
||
# Check third operand
|
||
if "operand3" in parse_result:
|
||
operands.append(self.process_operand(parse_result.operand3))
|
||
# Check fourth operand
|
||
if "operand4" in parse_result:
|
||
operands.append(self.process_operand(parse_result.operand4))
|
||
return_dict = InstructionForm(
|
||
mnemonic=parse_result.mnemonic,
|
||
operands=operands,
|
||
label_id=None,
|
||
comment_id=(
|
||
" ".join(parse_result[self.comment_id])
|
||
if self.comment_id in parse_result
|
||
else None
|
||
),
|
||
)
|
||
|
||
return return_dict
|
||
|
||
def parse_instruction(self, instruction):
|
||
"""
|
||
Parse instruction in asm line.
|
||
|
||
:param str instruction: Assembly line string.
|
||
:returns: `dict` -- parsed instruction form
|
||
"""
|
||
return self.make_instruction(
|
||
self.instruction_parser.parseString(instruction, parseAll=True)
|
||
)
|
||
|
||
def parse_register(self, register_string):
|
||
"""Parse register string"""
|
||
try:
|
||
return self.process_operand(self.register.parseString(register_string, parseAll=True))
|
||
except pp.ParseException:
|
||
return None
|
||
|
||
def process_operand(self, operand):
|
||
"""Post-process operand"""
|
||
if self.directive_id in operand:
|
||
return self.process_directive(operand[self.directive_id])
|
||
if self.identifier in operand:
|
||
return self.process_identifier(operand[self.identifier])
|
||
if self.immediate_id in operand:
|
||
return self.process_immediate(operand[self.immediate_id])
|
||
if self.label_id in operand:
|
||
return self.process_label(operand[self.label_id])
|
||
if self.memory_id in operand:
|
||
return self.process_memory_address(operand[self.memory_id])
|
||
if self.register_id in operand:
|
||
return self.process_register(operand[self.register_id])
|
||
return operand
|
||
|
||
def process_directive(self, directive):
|
||
# TODO: This is putting the identifier in the parameters. No idea if it's right.
|
||
parameters = [directive.identifier.name] if "identifier" in directive else []
|
||
parameters.extend(directive.parameters)
|
||
directive_new = DirectiveOperand(name=directive.name, parameters=parameters or None)
|
||
# Interpret the "=" directives because the generated assembly is full of symbols that are
|
||
# defined there.
|
||
if directive.name == "=":
|
||
self._equ[parameters[0]] = parameters[1]
|
||
return directive_new, directive.get("comment")
|
||
|
||
def process_register(self, operand):
|
||
return RegisterOperand(name=operand.name)
|
||
|
||
def process_register_expression(self, register_expression):
|
||
base = register_expression.get("base")
|
||
displacement = register_expression.get("displacement")
|
||
indexed = register_expression.get("indexed")
|
||
index = None
|
||
scale = 1
|
||
if indexed:
|
||
index = indexed.get("index")
|
||
scale = int(indexed.get("scale", "1"), 0)
|
||
if register_expression.get("operator_index") == "-":
|
||
scale *= -1
|
||
displacement_op = self.process_immediate(displacement.immediate) if displacement else None
|
||
if displacement_op and register_expression.get("operator_disp") == "-":
|
||
displacement_op.value *= -1
|
||
base_op = RegisterOperand(name=base.name) if base else None
|
||
index_op = RegisterOperand(name=index.name) if index else None
|
||
new_memory = MemoryOperand(
|
||
offset=displacement_op, base=base_op, index=index_op, scale=scale
|
||
)
|
||
return new_memory
|
||
|
||
def process_address_expression(self, address_expression, data_type=None):
|
||
# TODO: It seems that we could have a prefix immediate operand, a displacement in the
|
||
# brackets, and an offset. How all of this works together is somewhat mysterious.
|
||
immediate_operand = (
|
||
self.process_immediate(address_expression.immediate)
|
||
if "immediate" in address_expression
|
||
else None
|
||
)
|
||
register_expression = (
|
||
self.process_register_expression(address_expression.register_expression)
|
||
if "register_expression" in address_expression
|
||
else None
|
||
)
|
||
segment = (
|
||
self.process_register(address_expression.segment)
|
||
if "segment" in address_expression
|
||
else None
|
||
)
|
||
identifier = (
|
||
self.process_identifier(address_expression.identifier)
|
||
if "identifier" in address_expression
|
||
else None
|
||
)
|
||
if register_expression:
|
||
if immediate_operand:
|
||
register_expression.offset = immediate_operand
|
||
if data_type:
|
||
register_expression.data_type = data_type
|
||
return register_expression
|
||
elif segment:
|
||
return MemoryOperand(base=segment, offset=immediate_operand, data_type=data_type)
|
||
elif identifier:
|
||
if immediate_operand:
|
||
identifier.offset = immediate_operand
|
||
elif not data_type:
|
||
# An address expression without a data type or an offset is just an identifier.
|
||
# This matters for jumps.
|
||
return identifier
|
||
return MemoryOperand(offset=identifier, data_type=data_type)
|
||
else:
|
||
return MemoryOperand(base=immediate_operand, data_type=data_type)
|
||
|
||
def process_offset_expression(self, offset_expression):
|
||
# TODO: Record that this is an offset expression.
|
||
displacement = (
|
||
self.process_immediate(offset_expression.displacement)
|
||
if "displacement" in offset_expression
|
||
else None
|
||
)
|
||
if displacement and "operator_disp" == "-":
|
||
displacement.value *= -1
|
||
identifier = self.process_identifier(offset_expression.identifier)
|
||
identifier.offset = displacement
|
||
return MemoryOperand(offset=identifier)
|
||
|
||
def process_ptr_expression(self, ptr_expression):
|
||
# TODO: Do something with the data_type.
|
||
return self.process_address_expression(
|
||
ptr_expression.address_expression, ptr_expression.data_type
|
||
)
|
||
|
||
def process_short_expression(self, short_expression):
|
||
# TODO: Do something with the fact that it is short.
|
||
return LabelOperand(name=short_expression.identifier.name)
|
||
|
||
def process_memory_address(self, memory_address):
|
||
"""Post-process memory address operand"""
|
||
if "address_expression" in memory_address:
|
||
return self.process_address_expression(memory_address.address_expression)
|
||
elif "offset_expression" in memory_address:
|
||
return self.process_offset_expression(memory_address.offset_expression)
|
||
elif "ptr_expression" in memory_address:
|
||
return self.process_ptr_expression(memory_address.ptr_expression)
|
||
elif "short_expression" in memory_address:
|
||
return self.process_short_expression(memory_address.short_expression)
|
||
return memory_address
|
||
|
||
def process_label(self, label):
|
||
"""Post-process label asm line"""
|
||
# Remove duplicated 'name' level due to identifier. Note that there is no place to put the
|
||
# comment, if any.
|
||
label["name"] = label["name"]["name"]
|
||
return (
|
||
LabelOperand(name=label.name),
|
||
self.make_instruction(label) if "mnemonic" in label else None,
|
||
)
|
||
|
||
def process_immediate(self, immediate):
|
||
"""Post-process immediate operand"""
|
||
if "identifier" in immediate:
|
||
# Actually an identifier, change declaration.
|
||
return self.process_identifier(immediate.identifier)
|
||
new_immediate = ImmediateOperand(value=immediate.get("sign", "") + immediate.value)
|
||
new_immediate.value = self.normalize_imd(new_immediate)
|
||
return new_immediate
|
||
|
||
def process_identifier(self, identifier):
|
||
if identifier.name in self._equ:
|
||
# Actually an immediate, change declaration.
|
||
new_immediate = ImmediateOperand(
|
||
identifier=identifier.name, value=self._equ[identifier.name]
|
||
)
|
||
new_immediate.value = self.normalize_imd(new_immediate)
|
||
return new_immediate
|
||
return IdentifierOperand(name=identifier.name)
|
||
|
||
def normalize_imd(self, imd):
|
||
"""Normalize immediate to decimal based representation"""
|
||
if isinstance(imd.value, str):
|
||
if "." in imd.value:
|
||
return float(imd.value)
|
||
# Now parse depending on the base.
|
||
base = {"B": 2, "O": 8, "H": 16}.get(imd.value[-1], 10)
|
||
value = 0
|
||
negative = imd.value[0] == "-"
|
||
positive = imd.value[0] == "+"
|
||
start = +(negative or positive)
|
||
stop = len(imd.value) if base == 10 else -1
|
||
for c in imd.value[start:stop]:
|
||
value = value * base + int(c, base)
|
||
return -value if negative else value
|
||
else:
|
||
return imd.value
|