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d61330404b19bd72d14466a3786ded63dcc43081
OSACA/osaca/parser
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pleroy d61330404b Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle. 
I am completely restructuring the parser definition so that they are more explicit.  They are more verbose too, but at least I understand what they do.
2025-03-12 22:26:38 +01:00
..
__init__.py
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
base_parser.py
black formatting
2025-03-05 10:20:47 +01:00
condition.py
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
directive.py
Black formatting
2024-03-05 12:14:05 +01:00
flag.py
Black formatting
2024-03-05 12:14:05 +01:00
identifier.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
immediate.py
Flake8 formatting
2024-05-02 17:00:12 +02:00
instruction_form.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
label.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
memory.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
operand.py
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
parser_AArch64.py
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
parser_x86.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
parser_x86att.py
black formatting
2025-03-05 10:20:47 +01:00
parser_x86intel.py
Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle.
2025-03-12 22:26:38 +01:00
prefetch.py
added prefetch operand
2024-03-18 22:29:39 +01:00
register.py
fix #109
2024-10-01 12:00:47 +02:00