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ebf76caa18cd1c9ef4f8b61b41ca782c1f4b53a9
OSACA/osaca/parser
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Metehan Dundar ebf76caa18 Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames 
- Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support
- Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.)
- Renamed example files from rv6 to rv64 for consistency
- Updated related configuration and test files
- All 115 tests pass successfully
2025-07-11 18:15:51 +02:00
..
__init__.py
Merge branch 'master' into dev/risc-v
2025-05-08 12:23:22 +02:00
base_parser.py
Merge branch 'master' into dev/risc-v
2025-05-08 12:23:22 +02:00
condition.py
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
directive.py
Black formatting
2024-03-05 12:14:05 +01:00
flag.py
Black formatting
2024-03-05 12:14:05 +01:00
identifier.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
immediate.py
Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames
2025-07-11 18:15:51 +02:00
instruction_form.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
label.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
memory.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
operand.py
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
parser_AArch64.py
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
parser_RISCV.py
Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames
2025-07-11 18:15:51 +02:00
parser_x86.py
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
parser_x86att.py
black formatting
2025-03-05 10:20:47 +01:00
parser_x86intel.py
take +- operator of offset/index in mem-addr into account
2025-03-14 18:46:12 +01:00
prefetch.py
added prefetch operand
2024-03-18 22:29:39 +01:00
register.py
fix #109
2024-10-01 12:00:47 +02:00