Metehan Dundar
ebf76caa18
Apply selected improvements from 1ceac6e: enhanced RISC-V parser, ImmediateOperand enhancements, and rv6→rv64 file renames
...
- Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support
- Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.)
- Renamed example files from rv6 to rv64 for consistency
- Updated related configuration and test files
- All 115 tests pass successfully
2025-07-11 18:15:51 +02:00
Metehan Dundar
61b52dbf28
RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests
...
- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
2025-06-30 00:28:52 +02:00
Metehan Dundar
480c0dcac0
Merge branch 'master' into dev/risc-v
2025-05-08 12:23:22 +02:00
Metehan Dundar
aa3753d024
Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files
2025-05-08 11:57:06 +02:00
Metehan Dundar
d782f06e84
Add RISC-V support and update version to 0.6.2
2025-03-21 17:16:39 +01:00
JanLJL
31f5912af6
take +- operator of offset/index in mem-addr into account
2025-03-14 18:46:12 +01:00
pleroy
732dd95810
Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle.
...
I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.
2025-03-12 22:26:38 +01:00
JanLJL
ffb5f0eb55
Merge branch 'master' into merge-branch
2025-03-07 14:45:44 +01:00
JanLJL
bcecabd911
added support for <Xd>! registers and [<Xd>]! mem addresses in Arm
2025-03-07 11:49:14 +01:00
JanLJL
63f56e50b4
black formatting
2025-03-05 10:20:47 +01:00
JanLJL
fb7f1a289d
flake8 formatting
2025-03-05 10:19:10 +01:00
JanLJL
b6c3c924c6
remove dependency on MachineModel
2025-03-04 17:44:27 +01:00
JanLJL
1be2f320b9
add default syntax for get_parser for compatibility with kerncraft
2025-03-04 17:44:02 +01:00
JanLJL
379e422290
remove dependency on MachineModel
2025-03-04 17:42:52 +01:00
Metehan Dundar
7e546d970f
Parser for RISCV is implemented and tested with a
...
simple kernel.
Changes to be committed:
modified: osaca/parser/__init__.py
new file: osaca/parser/parser_RISCV.py
new file: tests/test_files/kernel_riscv.s
new file: tests/test_parser_RISCV.py
2025-03-04 00:44:38 +01:00
pleroy
b4d342266d
Add support for the Intel syntax supported by MSVC and ICC
2025-02-02 14:02:16 +01:00
JanLJL
602c0a9b71
fix #109
2024-10-01 12:00:47 +02:00
JanLJL
a63d23b13a
formatting
2024-08-19 15:50:37 +02:00
JanLJL
2fce0520d7
fixed bug in read-out of default store TP
2024-08-19 14:37:20 +02:00
Markus Büttner
14414fac01
Update parsing of memory segments
...
This addresses issue discussed in RRZE-HPC/OSACA#107 .
Now it can parse instructions of the form
%fs:var@RELOC
%fs:var@RELOC+4
%fs:var@RELOC(%rdi)
2024-07-30 16:02:16 +02:00
JanLJL
aeecac3b5f
Black formatting
2024-05-02 17:04:56 +02:00
JanLJL
a790ab7e79
Flake8 formatting
2024-05-02 17:00:12 +02:00
stefandesouza
ae2fcfe8bb
added prefetch operand
2024-03-18 22:29:39 +01:00
stefandesouza
e253638cb7
Black formatting
2024-03-05 12:14:05 +01:00
stefandesouza
4ec3788f58
Dump now converts classes to dicts
2024-03-05 00:18:45 +01:00
stefandesouza
62c21a7f31
Port pressure returned in tuple with Memory Operand
2024-03-04 20:00:43 +01:00
stefandesouza
d944c82d33
Immediate operand attribute name changes
2024-02-28 13:01:37 +01:00
stefandesouza
0474148d7b
Took out port pressure from Memory Operand. Gets() for LD/ST TP now use tupples
2024-02-24 21:03:15 +01:00
stefandesouza
6ce910e779
Took out name attribute from operand parent class
2024-02-24 15:46:04 +01:00
stefandesouza
d7768e5a8a
Removed comments from operands
2024-02-24 14:15:25 +01:00
stefandesouza
85677d1b0c
Flags into operand class
2024-02-24 12:11:52 +01:00
stefandesouza
d4eb7a9b72
Register attributes name change
2024-02-22 13:53:14 +01:00
stefandesouza
173f133241
Memory attributes name change
2024-02-22 13:51:48 +01:00
stefandesouza
bc7070cee2
Instruction form text change
2024-02-22 13:49:56 +01:00
stefandesouza
26918bad48
Made all attributes lower case
2024-02-22 13:48:56 +01:00
stefandesouza
9a7f38396f
Formatting before PR
2024-01-10 13:05:27 +01:00
stefandesouza
a2c67f1a61
Added shift and shift_op to Register Operand
2024-01-04 14:34:36 +01:00
stefandesouza
de6d8a1197
Small cleaup commit
2023-12-16 16:00:37 +01:00
stefandesouza
b8e88f9319
Merge remote-tracking branch 'origin/master' into InstrucForm
2023-12-16 12:14:36 +01:00
JanLJL
b7ff0b1461
bugfixes for SP reg and ccodes
2023-12-12 18:32:43 +01:00
stefandesouza
405a1d2857
Linters update
2023-12-10 18:25:00 +01:00
stefandesouza
47a44c9865
Workflow file includes new kenrcraft branch. Also changed checks for 'bad_operands' since they don't fit class style attributes
2023-12-10 17:26:43 +01:00
stefandesouza
1885ce6ddb
flake8 standards
2023-12-03 21:04:58 +01:00
stefandesouza
23d10d10cb
Black formatting
2023-12-03 17:22:11 +01:00
stefandesouza
62d575714a
Fixed semantic and marker tests. Now only dump needs to be adjusted
2023-12-03 16:49:33 +01:00
stefandesouza
37ca6670c7
pre/post-indexed to pre/post_indexed. Now have use ImmediateOperand type for mem offset. Changed some parser tests also
2023-12-02 16:56:43 +01:00
stefandesouza
78ca6fe855
Added condition operand, adjusted tests to parse it & a few changes to get the kernelDG tests working
2023-10-29 16:36:00 +01:00
stefandesouza
cce05e44cb
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
2023-10-29 13:52:49 +01:00
stefandesouza
46fc8c1f29
added a couple of attributes
2023-10-23 21:57:01 +02:00
stefandesouza
fad1997b76
Included 'source' and 'destination' attributes when loading isa data
2023-10-16 15:48:47 +02:00
