stm32/boards: Add alt-func CSV list and linker script for STM32F091.

This commit is contained in:
Damien George
2018-05-28 18:11:43 +10:00
parent ea7e747979
commit 1163400039
2 changed files with 115 additions and 0 deletions

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@@ -0,0 +1,89 @@
Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,,,,,,,,,
,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,,,,,,,,,ADC
PortA,PA0,,USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,USART4_TX,,,COMP1_OUT,,,,,,,,,ADC1_IN0
PortA,PA1,EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,USART4_RX,TIM15_CH1N,,,,,,,,,,,ADC1_IN1
PortA,PA2,TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,,,,,,,,,ADC1_IN2
PortA,PA3,TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,,,,,,,,,,,,,ADC1_IN3
PortA,PA4,SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,USART6_TX,,,,,,,,,,,ADC1_IN4
PortA,PA5,SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,,USART6_RX,,,,,,,,,,,ADC1_IN5
PortA,PA6,SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,USART3_CTS,TIM16_CH1,EVENTOUT,COMP1_OUT,,,,,,,,,ADC1_IN6
PortA,PA7,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,,,,,,,,,ADC1_IN7
PortA,PA8,MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,,,,,,,,,,,,
PortA,PA9,TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,,,,,,,,,,,
PortA,PA10,TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,,,,,,,,,,,,
PortA,PA11,EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN1_RX,I2C2_SCL,,COMP1_OUT,,,,,,,,,
PortA,PA12,EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN1_TX,I2C2_SDA,,COMP2_OUT,,,,,,,,,
PortA,PA13,SWDIO,IR_OUT,,,,,,,,,,,,,,,
PortA,PA14,SWCLK,USART2_TX,,,,,,,,,,,,,,,
PortA,PA15,SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,,,,,,,,,,,,
PortB,PB0,EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,,,,,,,,,,,,ADC1_IN8
PortB,PB1,TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,,,,,,,,,,,,ADC1_IN9
PortB,PB2,,,,TSC_G3_IO4,,,,,,,,,,,
PortB,PB3,SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,USART5_TX,,,,,,,,,,
PortB,PB4,SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,USART5_RX,TIM17_BKIN,,,,,,,,,
PortB,PB5,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,USART5_CK_RTS,,,,,,,,,,
PortB,PB6,USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,,,,,,,,,,,
PortB,PB7,USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,,,,,,,,,,
PortB,PB8,CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN1_RX,,,,,,,,,,
PortB,PB9,IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,CAN1_TX,SPI2_NSS/I2S2_WS,,,,,,,,,
PortB,PB10,CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,USART3_TX,SPI2_SCK/I2S2_CK,,,,,,,,,
PortB,PB11,EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,USART3_RX,,,,,,,,,,
PortB,PB12,SPI2_NSS/I2S2_WS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,USART3_CK,TIM15_BKIN,,,,,,,,,
PortB,PB13,SPI2_SCK/I2S2_CK,,TIM1_CH1N,TSC_G6_IO3,USART3_CTS,I2C2_SCL,,,,,,,,,
PortB,PB14,SPI2_MISO/I2S2_MCK,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,USART3_RTS,I2C2_SDA,,,,,,,,,
PortB,PB15,SPI2_MOSI/I2S2_SD,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,,,,,,,,,,,
PortC,PC0,EVENTOUT,USART7_TX,USART6_TX,,,,,,,,,,,,,,ADC1_IN10
PortC,PC1,EVENTOUT,USART7_RX,USART6_RX,,,,,,,,,,,,,,ADC1_IN11
PortC,PC2,EVENTOUT,SPI2_MISO/I2S2_MCK,USART8_TX,,,,,,,,,,,,,,ADC1_IN12
PortC,PC3,EVENTOUT,SPI2_MOSI/I2S2_SD,USART8_RX,,,,,,,,,,,,,,ADC1_IN13
PortC,PC4,EVENTOUT,USART3_TX,,,,,,,,,,,,,,,ADC1_IN14
PortC,PC5,TSC_G3_IO1,USART3_RX,,,,,,,,,,,,,,,ADC1_IN15
PortC,PC6,TIM3_CH1,USART7_TX,,,,,,,,,,,,,,,
PortC,PC7,TIM3_CH2,USART7_RX,,,,,,,,,,,,,,,
PortC,PC8,TIM3_CH3,USART8_TX,,,,,,,,,,,,,,,
PortC,PC9,TIM3_CH4,USART8_RX,,,,,,,,,,,,,,,
PortC,PC10,USART4_TX,USART3_TX,,,,,,,,,,,,,,,
PortC,PC11,USART4_RX,USART3_RX,,,,,,,,,,,,,,,
PortC,PC12,USART4_CK,USART3_CK,USART5_TX,,,,,,,,,,,,,,
PortC,PC13,,,,,,,,,,,,,,,,,
PortC,PC14,,,,,,,,,,,,,,,,,
PortC,PC15,,,,,,,,,,,,,,,,,
PortD,PD0,CAN1_RX,SPI2_NSS/I2S2_WS,,,,,,,,,,,,,,,
PortD,PD1,CAN1_TX,SPI2_SCK/I2S2_CK,,,,,,,,,,,,,,,
PortD,PD2,TIM3_ETR,USART3_RTS,USART5_RX,,,,,,,,,,,,,,
PortD,PD3,USART2_CTS,SPI2_MISO/I2S2_MCK,,,,,,,,,,,,,,,
PortD,PD4,USART2_RTS,SPI2_MOSI/I2S2_SD,,,,,,,,,,,,,,,
PortD,PD5,USART2_TX,,,,,,,,,,,,,,,,
PortD,PD6,USART2_RX,,,,,,,,,,,,,,,,
PortD,PD7,USART2_CK,,,,,,,,,,,,,,,,
PortD,PD8,USART3_TX,,,,,,,,,,,,,,,,
PortD,PD9,USART3_RX,,,,,,,,,,,,,,,,
PortD,PD10,USART3_CK,,,,,,,,,,,,,,,,
PortD,PD11,USART3_CTS,,,,,,,,,,,,,,,,
PortD,PD12,USART3_RTS,TSC_G8_IO1,USART8_CK_RTS,,,,,,,,,,,,,,
PortD,PD13,USART8_TX,TSC_G8_IO2,,,,,,,,,,,,,,,
PortD,PD14,USART8_RX,TSC_G8_IO3,,,,,,,,,,,,,,,
PortD,PD15,CRS_SYNC,TSC_G8_IO4,USART7_CK_RTS,,,,,,,,,,,,,,
PortE,PE0,TIM16_CH1,EVENTOUT,,,,,,,,,,,,,,,
PortE,PE1,TIM17_CH1,EVENTOUT,,,,,,,,,,,,,,,
PortE,PE2,TIM3_ETR,TSC_G7_IO1,,,,,,,,,,,,,,,
PortE,PE3,TIM3_CH1,TSC_G7_IO2,,,,,,,,,,,,,,,
PortE,PE4,TIM3_CH2,TSC_G7_IO3,,,,,,,,,,,,,,,
PortE,PE5,TIM3_CH3,TSC_G7_IO4,,,,,,,,,,,,,,,
PortE,PE6,TIM3_CH4,,,,,,,,,,,,,,,,
PortE,PE7,TIM1_ETR,USART5_CK_RTS,,,,,,,,,,,,,,,
PortE,PE8,TIM1_CH1N,USART4_TX,,,,,,,,,,,,,,,
PortE,PE9,TIM1_CH1,USART4_RX,,,,,,,,,,,,,,,
PortE,PE10,TIM1_CH2N,USART5_TX,,,,,,,,,,,,,,,
PortE,PE11,TIM1_CH2,USART5_RX,,,,,,,,,,,,,,,
PortE,PE12,TIM1_CH3N,SPI1_NSS/I2S1_WS,,,,,,,,,,,,,,,
PortE,PE13,TIM1_CH3,SPI1_SCK/I2S1_CK,,,,,,,,,,,,,,,
PortE,PE14,TIM1_CH4,SPI1_MISO/I2S1_MCK,,,,,,,,,,,,,,,
PortE,PE15,TIM1_BKIN,SPI1_MOSI/I2S1_SD,,,,,,,,,,,,,,,
PortF,PF0,CRS_SYNC,I2C1_SDA,,,,,,,,,,,,,,,
PortF,PF1,,I2C1_SCL,,,,,,,,,,,,,,,
PortF,PF2,EVENTOUT,USART7_TX,USART7_CK_RTS,,,,,,,,,,,,,,
PortF,PF3,EVENTOUT,USART7_RX,USART6_CK_RTS,,,,,,,,,,,,,,
PortF,PF6,,,,,,,,,,,,,,,,,
PortF,PF9,TIM15_CH1,USART6_TX,,,,,,,,,,,,,,,
PortF,PF10,TIM15_CH2,USART6_RX,,,,,,,,,,,,,,,
1 Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
2 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ADC
3 PortA PA0 USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 USART4_TX COMP1_OUT ADC1_IN0
4 PortA PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2 USART4_RX TIM15_CH1N ADC1_IN1
5 PortA PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3 COMP2_OUT ADC1_IN2
6 PortA PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4 ADC1_IN3
7 PortA PA4 SPI1_NSS/I2S1_WS USART2_CK TSC_G2_IO1 TIM14_CH1 USART6_TX ADC1_IN4
8 PortA PA5 SPI1_SCK/I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 USART6_RX ADC1_IN5
9 PortA PA6 SPI1_MISO/I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 USART3_CTS TIM16_CH1 EVENTOUT COMP1_OUT ADC1_IN6
10 PortA PA7 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT ADC1_IN7
11 PortA PA8 MCO USART1_CK TIM1_CH1 EVENTOUT CRS_SYNC
12 PortA PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1 I2C1_SCL MCO
13 PortA PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2 I2C1_SDA
14 PortA PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 CAN1_RX I2C2_SCL COMP1_OUT
15 PortA PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 CAN1_TX I2C2_SDA COMP2_OUT
16 PortA PA13 SWDIO IR_OUT
17 PortA PA14 SWCLK USART2_TX
18 PortA PA15 SPI1_NSS/I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT USART4_RTS
19 PortB PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2 USART3_CK ADC1_IN8
20 PortB PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3 USART3_RTS ADC1_IN9
21 PortB PB2 TSC_G3_IO4
22 PortB PB3 SPI1_SCK/I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1 USART5_TX
23 PortB PB4 SPI1_MISO/I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 USART5_RX TIM17_BKIN
24 PortB PB5 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA USART5_CK_RTS
25 PortB PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3
26 PortB PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4 USART4_CTS
27 PortB PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC CAN1_RX
28 PortB PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT CAN1_TX SPI2_NSS/I2S2_WS
29 PortB PB10 CEC I2C2_SCL TIM2_CH3 TSC_SYNC USART3_TX SPI2_SCK/I2S2_CK
30 PortB PB11 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1 USART3_RX
31 PortB PB12 SPI2_NSS/I2S2_WS EVENTOUT TIM1_BKIN TSC_G6_IO2 USART3_CK TIM15_BKIN
32 PortB PB13 SPI2_SCK/I2S2_CK TIM1_CH1N TSC_G6_IO3 USART3_CTS I2C2_SCL
33 PortB PB14 SPI2_MISO/I2S2_MCK TIM15_CH1 TIM1_CH2N TSC_G6_IO4 USART3_RTS I2C2_SDA
34 PortB PB15 SPI2_MOSI/I2S2_SD TIM15_CH2 TIM1_CH3N TIM15_CH1N
35 PortC PC0 EVENTOUT USART7_TX USART6_TX ADC1_IN10
36 PortC PC1 EVENTOUT USART7_RX USART6_RX ADC1_IN11
37 PortC PC2 EVENTOUT SPI2_MISO/I2S2_MCK USART8_TX ADC1_IN12
38 PortC PC3 EVENTOUT SPI2_MOSI/I2S2_SD USART8_RX ADC1_IN13
39 PortC PC4 EVENTOUT USART3_TX ADC1_IN14
40 PortC PC5 TSC_G3_IO1 USART3_RX ADC1_IN15
41 PortC PC6 TIM3_CH1 USART7_TX
42 PortC PC7 TIM3_CH2 USART7_RX
43 PortC PC8 TIM3_CH3 USART8_TX
44 PortC PC9 TIM3_CH4 USART8_RX
45 PortC PC10 USART4_TX USART3_TX
46 PortC PC11 USART4_RX USART3_RX
47 PortC PC12 USART4_CK USART3_CK USART5_TX
48 PortC PC13
49 PortC PC14
50 PortC PC15
51 PortD PD0 CAN1_RX SPI2_NSS/I2S2_WS
52 PortD PD1 CAN1_TX SPI2_SCK/I2S2_CK
53 PortD PD2 TIM3_ETR USART3_RTS USART5_RX
54 PortD PD3 USART2_CTS SPI2_MISO/I2S2_MCK
55 PortD PD4 USART2_RTS SPI2_MOSI/I2S2_SD
56 PortD PD5 USART2_TX
57 PortD PD6 USART2_RX
58 PortD PD7 USART2_CK
59 PortD PD8 USART3_TX
60 PortD PD9 USART3_RX
61 PortD PD10 USART3_CK
62 PortD PD11 USART3_CTS
63 PortD PD12 USART3_RTS TSC_G8_IO1 USART8_CK_RTS
64 PortD PD13 USART8_TX TSC_G8_IO2
65 PortD PD14 USART8_RX TSC_G8_IO3
66 PortD PD15 CRS_SYNC TSC_G8_IO4 USART7_CK_RTS
67 PortE PE0 TIM16_CH1 EVENTOUT
68 PortE PE1 TIM17_CH1 EVENTOUT
69 PortE PE2 TIM3_ETR TSC_G7_IO1
70 PortE PE3 TIM3_CH1 TSC_G7_IO2
71 PortE PE4 TIM3_CH2 TSC_G7_IO3
72 PortE PE5 TIM3_CH3 TSC_G7_IO4
73 PortE PE6 TIM3_CH4
74 PortE PE7 TIM1_ETR USART5_CK_RTS
75 PortE PE8 TIM1_CH1N USART4_TX
76 PortE PE9 TIM1_CH1 USART4_RX
77 PortE PE10 TIM1_CH2N USART5_TX
78 PortE PE11 TIM1_CH2 USART5_RX
79 PortE PE12 TIM1_CH3N SPI1_NSS/I2S1_WS
80 PortE PE13 TIM1_CH3 SPI1_SCK/I2S1_CK
81 PortE PE14 TIM1_CH4 SPI1_MISO/I2S1_MCK
82 PortE PE15 TIM1_BKIN SPI1_MOSI/I2S1_SD
83 PortF PF0 CRS_SYNC I2C1_SDA
84 PortF PF1 I2C1_SCL
85 PortF PF2 EVENTOUT USART7_TX USART7_CK_RTS
86 PortF PF3 EVENTOUT USART7_RX USART6_CK_RTS
87 PortF PF6
88 PortF PF9 TIM15_CH1 USART6_TX
89 PortF PF10 TIM15_CH2 USART6_RX

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@@ -0,0 +1,26 @@
/*
GNU linker script for STM32F091xC
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 256K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = _ebss; /* heap starts just after statically allocated memory */
_heap_end = 0x20006800; /* room for a 6k stack */