py/emitinlinerv32: Add Zba opcodes to the inline assembler.

This commit adds support for Zba opcodes to the RV32 inline assembler.

Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs
a scaled addition (by 1, 2, or 3 bits respectively).  At the moment only
qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these
opcodes (the latter only when using the RISCV variant).

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

tests/feature_check/inlineasm_rv32_zba.py

@@ -0,0 +1,10 @@
+# check if RISC-V 32 inline asm supported Zba opcodes
+
+
+@micropython.asm_rv32
+def f():
+    sh1add(a0, a0, a0)
+
+
+f()
+print("rv32_zba")

tests/feature_check/inlineasm_rv32_zba.py.exp

@@ -0,0 +1 @@
+rv32_zba

tests/inlineasm/rv32/asmzba.py

@@ -0,0 +1,18 @@
+@micropython.asm_rv32
+def test_sh1add(a0, a1):
+    sh1add(a0, a0, a1)
+
+
+@micropython.asm_rv32
+def test_sh2add(a0, a1):
+    sh2add(a0, a0, a1)
+
+
+@micropython.asm_rv32
+def test_sh3add(a0, a1):
+    sh3add(a0, a0, a1)
+
+
+print(hex(test_sh1add(10, 20)))
+print(hex(test_sh2add(10, 20)))
+print(hex(test_sh3add(10, 20)))

tests/inlineasm/rv32/asmzba.py.exp

@@ -0,0 +1,3 @@
+0x28
+0x3c
+0x64

tests/run-tests.py

@@ -816,6 +816,12 @@ def run_tests(pyb, tests, args, result_dir, num_threads=1):
                 skip_tests.add("inlineasm/thumb/asmfpmuldiv.py")
                 skip_tests.add("inlineasm/thumb/asmfpsqrt.py")
 
+        if args.inlineasm_arch == "rv32":
+            # Check if @micropython.asm_rv32 supports Zba instructions, and skip such tests if it doesn't
+            output = run_feature_check(pyb, args, "inlineasm_rv32_zba.py")
+            if output != b"rv32_zba\n":
+                skip_tests.add("inlineasm/rv32/asmzba.py")
+
         # Check if emacs repl is supported, and skip such tests if it's not
         t = run_feature_check(pyb, args, "repl_emacs_check.py")
         if "True" not in str(t, "ascii"):