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shared/runtime/gchelper: Add RISC-V RV32I native gchelper.

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Add native gchelper support for 32 bits RISC-V RV32I targets.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit is contained in:
Alessandro Gatti
2024-05-22 09:03:10 +02:00
committed by Damien George
parent e6ae699998
commit de0e13a9a8
3 changed files with 85 additions and 0 deletions
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2
shared/runtime/gchelper.h
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@@ -41,6 +41,8 @@ typedef uintptr_t gc_helper_regs_t[4];
typedef uintptr_t gc_helper_regs_t[10];
#elif defined(__aarch64__)
typedef uintptr_t gc_helper_regs_t[11]; // x19-x29
#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
typedef uintptr_t gc_helper_regs_t[12]; // S0-S11
#endif
#endif

31
shared/runtime/gchelper_generic.c
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@@ -150,6 +150,37 @@ static void gc_helper_get_regs(gc_helper_regs_t arr) {
arr[10] = x29;
}
#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
// Fallback implementation for RV32I, prefer gchelper_rv32i.s
static void gc_helper_get_regs(gc_helper_regs_t arr) {
register long s0 asm ("x8");
register long s1 asm ("x9");
register long s2 asm ("x18");
register long s3 asm ("x19");
register long s4 asm ("x20");
register long s5 asm ("x21");
register long s6 asm ("x22");
register long s7 asm ("x23");
register long s8 asm ("x24");
register long s9 asm ("x25");
register long s10 asm ("x26");
register long s11 asm ("x27");
arr[0] = s0;
arr[1] = s1;
arr[2] = s2;
arr[3] = s3;
arr[4] = s4;
arr[5] = s5;
arr[6] = s6;
arr[7] = s7;
arr[8] = s8;
arr[9] = s9;
arr[10] = s10;
arr[11] = s11;
}
#else
#error "Architecture not supported for gc_helper_get_regs. Set MICROPY_GCREGS_SETJMP to use the fallback implementation."

52
shared/runtime/gchelper_rv32i.s Normal file
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@@ -0,0 +1,52 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2024 Alessandro Gatti
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
.global gc_helper_get_regs_and_sp
.type gc_helper_get_regs_and_sp, @function
gc_helper_get_regs_and_sp:
/* Store registers into the given array. */
sw x8, 0(x10) /* Save S0. */
sw x9, 4(x10) /* Save S1. */
sw x18, 8(x10) /* Save S2. */
sw x19, 12(x10) /* Save S3. */
sw x20, 16(x10) /* Save S4. */
sw x21, 20(x10) /* Save S5. */
sw x22, 24(x10) /* Save S6. */
sw x23, 28(x10) /* Save S7. */
sw x24, 32(x10) /* Save S8. */
sw x25, 36(x10) /* Save S9. */
sw x26, 40(x10) /* Save S10. */
sw x27, 44(x10) /* Save S11. */
/* Return the stack pointer. */
add x10, x0, x2
jalr x0, x1, 0
.size gc_helper_get_regs_and_sp, .-gc_helper_get_regs_and_sp