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stm32/main: Enable all AHB5 GRP1 clocks in low power mode.

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The main functional change here is to make sure that the SDMMC1/2 clocks
are enabled in low power mode; they were not previously enabled for SD card
use, only WLAN.  It doesn't hurt to unconditionally enable the clocks in
low power, like all the other peripherals.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George
2025-12-17 14:39:06 +11:00
parent 07540a8fd1
commit e48b98537f
4 changed files with 1 additions and 12 deletions
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5
ports/stm32/eth.c
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@@ -370,11 +370,6 @@ static int eth_mac_init(eth_t *self) {
__HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE();
#elif defined(STM32N6)
__HAL_RCC_ETH1_RELEASE_RESET();
__HAL_RCC_ETH1_CLK_SLEEP_ENABLE();
__HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE();
__HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE();
__HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE();
#else
__HAL_RCC_ETHMAC_RELEASE_RESET();

2
ports/stm32/main.c
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@@ -409,13 +409,13 @@ void stm32_main(uint32_t reset_mode) {
LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM1 | LL_MEM_AXISRAM2 | LL_MEM_AXISRAM3
| LL_MEM_AXISRAM4 | LL_MEM_AXISRAM5 | LL_MEM_AXISRAM6 | LL_MEM_AHBSRAM1 | LL_MEM_AHBSRAM2
| LL_MEM_BKPSRAM | LL_MEM_FLEXRAM | LL_MEM_CACHEAXIRAM | LL_MEM_VENCRAM | LL_MEM_BOOTROM);
LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2 | LL_AHB5_GRP1_PERIPH_XSPIM);
LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTC | LL_APB4_GRP1_PERIPH_RTCAPB);
LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTC | LL_APB4_GRP1_PERIPH_RTCAPB);
// Enable some AHB peripherals during sleep.
LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ALL); // GPDMA1, ADC12
LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_ALL); // GPIOA-Q, PWR, CRC
LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ALL); // DMA2D, ETH, FMC, GFXMMU, GPU2D, HPDMA, XSPI, JPEG, MCE, CACHEAXI, NPU, OTG, PSSI, SDMMC
// Enable some APB peripherals during sleep.
LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_ALL); // I2C, I3C, LPTIM, SPI, TIM, UART, WWDG

4
ports/stm32/sdio.c
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@@ -131,10 +131,6 @@ void sdio_init(uint32_t irq_pri) {
mp_hal_pin_config_alt_static(MICROPY_HW_SDIO_CMD, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, STATIC_AF_SDMMC_CMD);
SDMMC_CLK_ENABLE(); // enable SDIO peripheral
#if defined(STM32N6)
LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1);
LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2);
#endif
SDMMC_TypeDef *SDIO = SDMMC;
#if defined(STM32F7)

2
ports/stm32/usbd_conf.c
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@@ -279,8 +279,6 @@ static void mp_usbd_ll_init_hs(void) {
LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG1);
LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1);
LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1);
LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1);
// Select 24MHz clock.
MODIFY_REG(USB1_HS_PHYC->USBPHYC_CR, USB_USBPHYC_CR_FSEL, 2 << USB_USBPHYC_CR_FSEL_Pos);