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4622 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Phil Howard
|
11f057dd9a |
rp2: Add support for PSRAM with auto-detection.
Performs a best-effort attempt to detect attached PSRAM, configure it and *add* it to the MicroPython heap. If PSRAM is not present, should fall back to use internal RAM. Introduce two new port/board defines: - MICROPY_HW_ENABLE_PSRAM to enable PSRAM. - MICROPY_HW_PSRAM_CS_PIN to define the chip-select pin (required). Changes are: - ports/rp2/rp2_psram.[ch]: Add new PSRAM module. - ports/rp2/main.c: Add optional PSRAM support. - ports/rp2/CMakeLists.txt: Include rp2_psram.c. - ports/rp2/mpconfigport.h: Add MICROPY_HW_ENABLE_PSRAM. - ports/rp2/modmachine.c: Reconfigure PSRAM on freq change. Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com> Co-authored-by: Mike Bell <mike@mercuna.com> Signed-off-by: Phil Howard <phil@gadgetoid.com> |
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Alessandro Gatti
|
6bb586619d |
esp32/esp32_common.cmake: Remove obsolete definition.
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This commit removes a definition used back when ESP-IDF v4 was supported by MicroPython. Those times are now long gone, and so is the need for that particular definition to be set in the first place. Signed-off-by: Alessandro Gatti <a.gatti@frob.it> |
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|
Alessandro Gatti
|
fda9bf4917 |
esp32/esp32_common.cmake: Clean up RISC-V directives.
This commit cleans up a couple of RISC-V specific directives in the build script. Namely, removes the forced inclusion of the "riscv" component and introduces proper mpy-cross flags. The "riscv" component is already included by the ESP-IDF build framework, as certain low-level components would not build otherwise, so there is no need to add it to the required components list. The architecture flag for mpy-cross is now set for RISC-V targets, as it was previously set only for Xtensa targets (and it relied on a string comparison rather than using the appropriate configuration variable). Signed-off-by: Alessandro Gatti <a.gatti@frob.it> |
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Alessandro Gatti
|
9ab6906f50 |
esp32/esp32_common.cmake: Use native gchelper for RISC-V.
This commit changes the gchelper implementation in use for RV32-based targets (ESP32C3, ESP32C6) from the generic one written in C to the one written in assembler that is specific to the CPU in question. The native implementation is already exercised on most CI builds as it is used by the QEMU port to compile and test the RV32 target. Signed-off-by: Alessandro Gatti <a.gatti@frob.it> |
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Damien George
|
1660faacf6 |
stm32/boards/PYBD_SF2: Restart qspi memory-mapped mode during startup.
The PYBD boards use an F7xx which has an errata 2.4.3:
Memory-mapped read operations may fail when timeout counter is enabled
This is unfortunate because it means that once QSPI memory-mapped flash is
accessed the QSPI peripheral will leave the CS pin active (low) forever,
which increases power consumption of the SPI flash chip (because it's
active and waiting for commands). The exact amount of power increase
depends on the flash, but the PYBD_SFx increase by about 2.5mA.
Previously this increase in power only happened when QSPI flash was needed,
eg on PYBD_SF2 when mbedtls or nimble libraries were used. On PYBD_SF6
it's actually never used.
But with the introduction of ROMFS which lives in the QSPI flash, the
memory is always access on start up to see if the ROMFS contains a valid
image (it must read the memory to find out). That means these boards
always consume about 2.5mA more after starting up (compared to when ROMFS
is disabled).
The fix in this commit is to explicitly restart the QSPI memory mapped mode
during the start up process. More precisely, the restart is done after
querying the ROMFS and just before trying to execute `boot.py`. That's the
right location to keep power consumption permanently down if the QSPI is
never used (eg ROMFS image doesn't exist).
Signed-off-by: Damien George <damien@micropython.org>
|
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Damien George
|
ac1cbef366 |
stm32/qspi: Add qspi_memory_map_exit and restart.
Signed-off-by: Damien George <damien@micropython.org> |
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Matt Trentini
|
c18e925431 |
stm32/timer: Add support for STM32H5 Timer 1.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com> |
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Herwin Grobben
|
91386b3d56 |
stm32/timer: Use APB2 to calculate timer 20 source frequency.
Signed-off-by: Herwin Grobben <h.grobben@aemics.nl> |
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Herwin Grobben
|
3b948893d8 |
stm32/stm32_it: Add handler for timer 20 interrupt.
Signed-off-by: Herwin Grobben <h.grobben@aemics.nl> |
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iabdalkader
|
1a47379dd6 |
stm32/boards: Add F427 AF CSV file.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com> |
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Andrew Leech
|
b33b9f8121 |
stm32/main: Catch and report corrupted lfs filesystem at startup.
On stm32, the startup code attempts to mount the configured filesystem. If
there is an existing littlefs filesystem that's suitable corrupted it's
possible for the reported blocksize to be incorrect here:
uint32_t block_size = lfs2_fromle32(superblock->block_size);
This `block_size` (which is read from the filesystem iteself) is used to
create the len argument passed to `pyb_flash_make_new()`. In that function
the len arg is validated to be a mutliple of the underlying hardware block
size, as well as not bigger than the physical flash. Any failure is raised
as a ValueError. This exception is not caught currently in main, it flows
up to the high level assert / startup failure.
As this occurs before `boot.py` is run, the users (potentially frozen)
application code doesn't have any opportunity to detect and handle the
issue.
This commit adds a helper function which attempts to create a block device,
and on error returns `None` instead of raising an exception. Using this in
main means that a potentially corrupt filesystem will simply remain
unmounted, and the application can handle the issue safely.
The fix here also handles the case where the littlefs filesystem is valid
but the autodetection code (which detects the filesystem size) does not
work correctly. In that case it will retry mounting the filesystem using
the whole size of the block device.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
|
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Mark Seminatore
|
f96417dbf2 |
rp2/cyw43_configport: Fix cyw43 mDNS by properly starting mDNS on netif.
The rp2 port has an incomplete mDNS implementation. The code in `main.c` calls `mdns_resp_init()` which opens the UDP socket for mDNS. However, no code in the cyw43 driver makes the proper calls to `mdns_resp_add_netif()` and `mdns_resp_remove_netif()` to send the announce packets. The wiznet5k driver does make these calls and was used as a model for these changes. This commit attempts to address this by very small changes to the `ports/rp2/cyw43_configport.h` file. The change uses new cyw43 driver hooks to map the driver macros `CYW43_CB_TCPIP_INIT_EXTRA` and `CYW43_CB_TCPIP_DEINIT_EXTRA` to the appropriate lwIP mDNS calls. Fixes issue #15297. Signed-off-by: Mark Seminatore <nebula_peeps4t@icloud.com> |
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|
Damien George
|
5eee5a67dc |
rp2/Makefile: Use $(Q) prefix on all commands.
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This prevents printing the lengthy command and makes the build output a little cleaner. Signed-off-by: Damien George <damien@micropython.org> |
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Damien George
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a828b99cff |
esp32/Makefile: Use $(Q) prefix on all commands.
This prevents printing the lengthy command and makes the build output a little cleaner. Signed-off-by: Damien George <damien@micropython.org> |
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Angus Gratton
|
50da085d93 |
rp2: Print an error message if pico-sdk submodule is missing.
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This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au> |
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Angus Gratton
|
cccac2cc01 |
rp2,esp32,extmod: Implement UPDATE_SUBMODULES in CMake.
Rather than having Make calling CMake to generate a list of submodules and then run a Make target (which is complex and prone to masking other errors), implement the submodule update logic in CMake itself. Internal CMake-side changes are that GIT_SUBMODULES is now a CMake list, and the trigger variable name is changed from ECHO_SUBMODULES to UPDATE_SUBMODULES. The run is otherwise 100% a normal CMake run now, so most of the other special casing can be removed. Signed-off-by: Angus Gratton <angus@redyak.com.au> |
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robert-hh
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4dfee50a0b |
samd/machine_uart: Fix lock-up in loopback mode if read buffer is full.
Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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6db7b47ab9 |
samd/machine_uart: Fix unintended UART buffer allocation on init().
The buffer was be reset on every call to uart.init(). If no sizes were given, the buffer was set to the default size 256. That made problems e.g. with PPP. This commit fixes it, keeping the buffer size if not deliberately changed and allocating new buffers only if the size was changed. Cater for changes of the bits value, which requires a change to the buffer size. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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2b2a431878 |
rp2/machine_uart: Fix unintended UART buffer allocation on init().
The buffer was be reset on every call to uart.init(). If no sizes were given, the buffer was set to the default size 256. That made problems e.g. with PPP. This commit fixes it, keeping the buffer size if not deliberately changed and allocating new buffers only if the size was changed. Signed-off-by: robert-hh <robert@hammelrath.com> |
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Angus Gratton
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35d4d2d06b |
rp2/pendsv: Account for PendSV running on both cores, and without CYW43.
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Changes: - Move setting of PendSV priority to pendsv_init(). - Call pendsv_init() from CPU1 as well, to ensure priority is the same. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au> |
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Angus Gratton
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23fb171b80 |
rp2/mpnetworkport: Refactor out cyw43_has_pending global variable.
A better indication of whether a cyw43 event is pending is the actual flag in the PendSV handler table. (If this fails, could also use the GPIO interrupt enabled register bit). This commit was needed of a previous version of the fix in the parent commit, but it turned out not strictly necessary for the current version. However, it's still a good clean up. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au> |
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Angus Gratton
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6fa498cba1 |
rp2/mpnetworkport: Fix lost CYW43 WiFi events when using both cores.
There's a very odd but predictable sequence of events that breaks Wi-Fi when using both cores: 1) CPU1 calls pendsv_suspend() - for example sleep() causes a softtimer node to be inserted, which calls pendsv_suspend(). 2) CYW43 sends wakeup IRQ. CPU0 GPIO IRQ handler schedules PendSV and disables the GPIO IRQ on CPU0, to re-enable after cyw43_poll() runs and completes. 3) CPU0 PendSV_Handler runs, sees pendsv is suspended, exits. 4) CPU1 calls pendsv_resume() and pendsv_resume() sees PendSV is pending and triggers it on CPU1. 5) CPU1 runs PendSV_Handler, runs cyw43_poll(), and at the end it re-enables the IRQ *but now on CPU1*. However CPU1 has GPIO IRQs disabled, so the CYW43 interrupt never runs again... The fix in this commit is to always enable/disable the interrupt on CPU0. This isn't supported by the pico-sdk, but it is supported by the hardware. Fixes issue #16779. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au> |
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Phil Howard
|
dd7a950bbc |
rp2/machine_spi: Allow MISO to be unspecified.
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It's common with write-only SPI displays for MISO to be repurposed as a register select or data/command pin. While that was possible by setting up the pin after a call to `machine.SPI()` this change makes `machine.SPI(miso=None)` explicit. Signed-off-by: Phil Howard <github@gadgetoid.com> |
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Phil Howard
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a86122396d |
rp2/machine_spi: Make SPI ID optional.
If the "spi_id" arg is not supplied and then the board default specified by PICO_DEFAULT_SPI will be used. Signed-off-by: Phil Howard <github@gadgetoid.com> |
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Phil Howard
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f315a376b6 |
rp2/machine_i2c: Require an I2C bus ID when no default is available.
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When PICO_DEFAULT_I2C is not set require an I2C bus ID instead of
using -1 as a default, which would fail with a cryptic:
"I2C(-1) doesn't exist"
Signed-off-by: Phil Howard <github@gadgetoid.com>
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Malcolm McKellips
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93a8c53d64 |
rp2/boards/SPARKFUN_IOTNODE_LORAWAN_RP2350: Add SD card support.
The IOTNODE_LORAWAN_RP2350 has an SD card and we want users to be able to `import sdcard` without copying `sdcard.py` over to their board. Signed-off-by: Malcolm McKellips <malcolm.mckellips@sparkfun.com> |
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Malcolm McKellips
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1e92bdd206 |
rp2/boards: Fix SparkFun vendor name.
The preferred/correct spelling is "SparkFun" so this commit updates all of the existing SparkFun board definitions with that spelling. |
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Damien George
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396ab268df |
stm32/qspi: Implement MP_QSPI_IOCTL_MEMORY_MODIFIED ioctl.
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stm32's QSPI driver supports memory-mapped mode. The memory-mapped flash can also be erased/written to. To support both these modes, it switches in and out of memory-mapped mode during an erase/write. If the flash is erased/written and then switched back to memory mapped mode, the cache related to the memory-mapped region that changed must be invalidated. Otherwise subsequent code may end up reading old data. That cache invalidation is currently not being done, and this commit fixes that. This bug has been around ever since QSPI memory-mapped mode existed, but it's never really been observed because it's not common to use flash in memory-mapped mode and also erase/write it. Eg PYBD_SF2 uses the memory-mapped flash in read-only mode to store additional firmware. But since the introduction of ROMFS, things changed. The `vfs.rom_ioctl()` command can erase/write memory-mapped flash. Signed-off-by: Damien George <damien@micropython.org> |
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Damien George
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c61e859108 |
drivers: Add MP_QSPI_IOCTL_MEMORY_MODIFIED to indicate flash changed.
Signed-off-by: Damien George <damien@micropython.org> |
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robert-hh
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274c8c419c |
mimxrt/boards: Update deploy instructions.
Make the final step of the deploy more detailed. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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cdcc70d4f8 |
mimxrt: Enable default devices for I2C, SPI and UART.
Since all boards are configured to have a I2C(0), SPI(0) and UART(1), these can be set as default devices, allowing the instantiation of I2C(), SPI(), UART() without an id argument. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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1e7328ca28 |
mimxrt/machine_i2c: Support the timeout keyword argument.
Set the default timeout to 50000 us. The default used to be 0, causing the NXP I2C driver to silently stop working in case of a non-responding device. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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b85ad4bd41 |
mimxrt/machine_uart: Fix rx/tx buffer allocation bug.
The buffer would be reset on every call to `uart.init()`. If no sizes were given, the buffer would be set to the default size 256. That made problems e.g. with PPP. Also, the RX buffer was not stored at the UART object and not visible to GC as being in use. Then a `gc.collect()` would eventually free the buffer. This commit fixes those issues, keeping the buffer size if not deliberately changed and allocating new buffers only if the size was changed. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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1398e7fd20 |
mimxrt/hal/qspi_nor_flash_config: Use a safe common CS timing.
The flash devices used by the MIMXRT board are specified either with 3ns or 5 ns CS setup and hold time. Since a single configuration file is used for all boards, use 5ns instead of 3ns to be safe, even if there were no problems so far. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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2d20dbce2c |
mimxrt/machine_uart: Remove duplicate init and make IRQ optional.
Changes: - The duplicate LPUART_Init call was not needed, just an edit fail. - Allow a port to disable UART.irq(). Some code for configuration stays, but the respective UART IRQ is not enabled. Calling uart.irq() will cause an exception by extmod/machine_uart.c. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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2a5b97beae |
mimxrt/mpconfigport: Enable PPP for boards with lwIP.
PPP is now enabled on all boards with Ethernet support. PPP could be enabled for other boards without Ethernet like the Teensy 4.0 as well in a second step. Enabling for MIMXRT101x boards is hardly possible due to the large RAM demand of lwIP. Tested with a Teensy 4.1 board and a SimCom A7608 GPRS/LTE modem. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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d8edae040f |
mimxrt/mpconfigport: Enable support for exFAT.
There is plenty of room in the MIMXRT board flash, so it can be enabled. Tested with: - MIMXRT1176_EVK - MIMXRT1061 (Teensy 4.1) - MIMXRT1010 (Olimex RT1010) Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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58f1ade318 |
mimxrt/machine_adc: Add ADC.read_uv() method.
Matching the generic documentation. Signed-off-by: robert-hh <robert@hammelrath.com> |
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robert-hh
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f1018ee5c2 |
mimxrt/boards/MAKERDIARY_RT1011_NANO_KIT: Add new Makerdiary board.
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This is a board based on the i.MX RT1011 in breadboard-friendly shape. A good basic board with 16M flash and regular pinout, providing access to many GPIO_nn and GPIO_AD_nn Pins. Signed-off-by: robert-hh <robert@hammelrath.com> |
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Angus Gratton
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9db2398009 |
stm32/can: Refactor can.h API to not depend on pyboard can types.
This is necessary for the machine.CAN implementation to use the same low-level functions. Includes some refactoring around FIFO selection as there was a footgun where CAN_FIFO0/1 are 0/1 but FDCAN_RX_FIFO0/1 are not. Added an explicit type for non-hardware-specific FIFO numbering. Also moved responsibility for re-enabling CAN receive interrupts into the higher layer (pyb_can.c layer) after calling can_receive(). Also includes this behaviour change for FDCAN boards: - Fix for boards with FDCAN not updating error status counters (num_error_warning, num_error_passive, num_bus_off). These are now updated the same as on boards with CAN Classic controllers, as documented. - Previously FDCAN boards would trigger the RX callback function on error events instead (passing undocumented irq numbers 3, 4, 5). This behaviour has been removed in favour of the documented behaviour of updating the status counters. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au> |
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iabdalkader
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96ce08e498 |
stm32/boards/ARDUINO_PORTENTA_H7: Enable 4MiB ROMFS part in ext flash.
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com> |
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iabdalkader
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edc927a185 |
stm32/boards/ARDUINO_NICLA_VISION: Enable 4MiB ROMFS part in ext flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com> |
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iabdalkader
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043dc79592 |
stm32/boards/ARDUINO_GIGA: Enable 4MiB ROMFS partition in ext flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com> |
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Damien George
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d5aeca2e83 |
esp8266: Rename ROMFS partition config variables to include "part0".
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For consistency with the stm32 port. Signed-off-by: Damien George <damien@micropython.org> |
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Damien George
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bf9cdd2189 |
stm32: Rename ROMFS partition config variables to start at index 0.
Change ROMFS partition configuration variables to use index 0 as the starting partition number (instead of index 1). Reasons to do this: - `vfs.rom_ioctl()` numbers the partitions starting from 0 - `mpremote romfs -p <partition id>` numbers the partitions starting from 0 Signed-off-by: Damien George <damien@micropython.org> |
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Lesords
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416c6cf0c8 |
rp2/boards/SEEED_XIAO_RP2350: Add new Seeed XIAO board definition.
Signed-off-by: Lesords <2385342343@qq.com> |
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Dryw Wade
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2264340559 |
rp2/boards/SPARKFUN_XRP_CONTROLLER_BETA: Fix XRP Controller Beta URL.
Signed-off-by: Dryw Wade <dryw.wade@sparkfun.com> |
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Dryw Wade
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ac30dcb20c |
rp2/boards/SPARKFUN_XRP_CONTROLLER: Add SparkFun XRP Controller.
Signed-off-by: Dryw Wade <dryw.wade@sparkfun.com> |
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Matt Trentini
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8dcf9290f8 |
rp2/boards/WEACTSTUDIO_RP2350B_CORE: Add WeAct Studio RP2350B Core.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com> |
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Alex Brudner
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9a070fee34 |
rp2/boards/SPARKFUN_IOTREDBOARD_RP2350: Add support for IoT RedBoard.
Signed-off-by: Alex Brudner <alex.brudner@sparkfun.com> Signed-off-by: Malcolm McKellips <malcolm.mckellips@sparkfun.com> |