docs: Bump version to 1.8.4.

It has reliability issues (cause unknown at this time).

.gitattributes

@@ -0,0 +1,31 @@
+# Per default everything gets normalized and gets LF line endings on checkout.
+* text eol=lf
+
+# These will always have CRLF line endings on checkout.
+*.vcxproj text eol=crlf
+*.props text eol=crlf
+*.bat text eol=crlf
+
+# These are binary so should never be modified by git.
+*.png binary
+*.jpg binary
+*.dxf binary
+
+# These should also not be modified by git.
+tests/basics/string_cr_conversion.py -text
+tests/basics/string_crlf_conversion.py -text
+stmhal/startup_stm32f40xx.s -text
+stmhal/pybcdc.inf_template -text
+stmhal/usbd_* -text
+stmhal/boards/*/stm32f4xx_hal_conf.h -text
+stmhal/cmsis/** -text
+stmhal/hal/** -text
+stmhal/usbdev/** -text
+stmhal/usbhost/** -text
+cc3200/hal/aes.c -text
+cc3200/hal/aes.h -text
+cc3200/hal/des.c -text
+cc3200/hal/i2s.c -text
+cc3200/hal/i2s.h -text
+cc3200/version.h -text
+lib/fatfs/** -text

.gitignore

@@ -32,3 +32,9 @@ tests/*.out
 # Python cache files
 ######################
 __pycache__/
+*.pyc
+
+# Customized Makefile/project overrides
+######################
+GNUmakefile
+user.props

.gitmodules

@@ -0,0 +1,13 @@
+[submodule "lib/axtls"]
+	path = lib/axtls
+	url = https://github.com/pfalcon/axtls
+	branch = micropython
+[submodule "lib/libffi"]
+	path = lib/libffi
+	url = https://github.com/atgreen/libffi
+[submodule "lib/lwip"]
+	path = lib/lwip
+	url = http://git.savannah.gnu.org/r/lwip.git
+[submodule "lib/berkeley-db-1.xx"]
+	path = lib/berkeley-db-1.xx
+	url = https://github.com/pfalcon/berkeley-db-1.xx

.travis.yml

@@ -1,21 +1,56 @@
+sudo: required
+dist: trusty
 language: c
 compiler:
   - gcc
 
 before_script:
-  - sudo add-apt-repository -y ppa:fkrull/deadsnakes
-  - sudo add-apt-repository -y ppa:ubuntu-toolchain-r/test
+# Extra CPython versions
+#  - sudo add-apt-repository -y ppa:fkrull/deadsnakes
+# Extra gcc versions
+#  - sudo add-apt-repository -y ppa:ubuntu-toolchain-r/test
   - sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded
-  - sudo apt-get update -qq
-  - sudo apt-get install -y python3.3 python3 gcc-4.7 gcc-arm-none-eabi qemu-system
+  - sudo dpkg --add-architecture i386
+  - sudo apt-get update -qq || true
+  - sudo apt-get install -y python3 gcc-multilib pkg-config libffi-dev libffi-dev:i386 qemu-system mingw32
+  - sudo apt-get install -y --force-yes gcc-arm-none-eabi
+  # For teensy build
+  - sudo apt-get install realpath
+  # For coverage testing
+  - sudo pip install cpp-coveralls
+  - gcc --version
+  - arm-none-eabi-gcc --version
+  - python3 --version
 
 script:
-  - make -C unix CC=gcc-4.7
-  - make -C unix-cpy CC=gcc-4.7
+  - make -C mpy-cross
+  - make -C minimal test
+  - make -C unix deplibs
+  - make -C unix
+  - make -C unix nanbox
   - make -C bare-arm
-  - make -C qemu-arm
+  - make -C qemu-arm test
   - make -C stmhal
-  - (cd tests && MICROPY_CPYTHON3=python3.3 ./run-tests)
+  - make -C stmhal -B MICROPY_PY_WIZNET5K=1 MICROPY_PY_CC3K=1
+  - make -C stmhal BOARD=STM32F4DISC
+  - make -C teensy
+  - make -C cc3200 BTARGET=application BTYPE=release
+  - make -C cc3200 BTARGET=bootloader  BTYPE=release
+  - make -C windows CROSS_COMPILE=i586-mingw32msvc-
+
+  # run tests without coverage info
+  #- (cd tests && MICROPY_CPYTHON3=python3.4 ./run-tests)
+  #- (cd tests && MICROPY_CPYTHON3=python3.4 ./run-tests --emit native)
+
+  # run tests with coverage info
+  - make -C unix coverage
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests)
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests -d thread)
+  - (cd tests && MICROPY_CPYTHON3=python3.4 MICROPY_MICROPYTHON=../unix/micropython_coverage ./run-tests --emit native)
+
+after_success:
+  - (cd unix && coveralls --root .. --build-root . --gcov $(which gcov) --gcov-options '\-o build-coverage/' --include py --include extmod)
 
 after_failure:
-  - (cd tests && for exp in *.exp; do testbase=$(basename $exp .exp); echo -e "\nFAILURE $testbase"; diff $testbase.exp $testbase.out; done)
+  - (cd tests && for exp in *.exp; do testbase=$(basename $exp .exp); echo -e "\nFAILURE $testbase"; diff -u $testbase.exp $testbase.out; done)
+  - (grep "FAIL" qemu-arm/build/console.out)

CODECONVENTIONS.md

@@ -1,3 +1,31 @@
+Git commit conventions
+======================
+
+Each commit message should start with a directory or full file path
+prefix, so it was clear which part of codebase a commit affects. If
+a change affects one file, it's better to use path to a file. If it
+affects few files in a subdirectory, using subdirectory as a prefix
+is ok. For longish paths, it's acceptable to drop intermediate
+components, which still should provide good context of a change.
+It's also ok to drop file extensions.
+
+Besides prefix, first line of a commit message should describe a
+change clearly and to the point, and be a grammatical sentence with
+final full stop. First line should fit within 78 characters. Examples
+of good first line of commit messages:
+
+    py/objstr: Add splitlines() method.
+    py: Rename FOO to BAR.
+    docs/machine: Fix typo in reset() description.
+    ports: Switch to use lib/foo instead of duplicated code.
+
+After the first line, add an empty line and in following lines describe
+a change in a detail, if needed. Any change beyond 5 lines would likely
+require such detailed description.
+
+To get good practical examples of good commits and their messages, browse
+thry the `git log` of the project.
+
 Python code conventions
 =======================
 
@@ -33,26 +61,50 @@ Braces:
   closing brace.
 
 Header files:
-- Try to stick to the Plan 9 header style, where header files do not
-  include other header files.
-- Don't protect a header file from multiple inclusion with #if directives.
+- Header files should be protected from multiple inclusion with #if
+  directives. See an existing header for naming convention.
 
-Type names and declarations:
-- When defining a type, put '_t' after it.
+Names:
+- Use underscore_case, not camelCase for all names.
+- Use CAPS_WITH_UNDERSCORE for enums and macros.
+- When defining a type use underscore_case and put '_t' after it.
+
+Integer types: MicroPython runs on 16, 32, and 64 bit machines, so it's
+important to use the correctly-sized (and signed) integer types.  The
+general guidelines are:
+- For most cases use mp_int_t for signed and mp_uint_t for unsigned
+  integer values.  These are guaranteed to be machine-word sized and
+  therefore big enough to hold the value from a MicroPython small-int
+  object.
+- Use size_t for things that count bytes / sizes of objects.
+- You can use int/uint, but remember that they may be 16-bits wide.
+- If in doubt, use mp_int_t/mp_uint_t.
+
+Comments:
+- Be concise and only write comments for things that are not obvious.
+- Use `// ` prefix, NOT `/* ... */`. No extra fluff.
+
+Memory allocation:
+- Use m_new, m_renew, m_del (and friends) to allocate and free heap memory.
+  These macros are defined in py/misc.h.
 
 Examples
 --------
 
-Braces and spaces:
+Braces, spaces, names and comments:
 
-    int foo(int x, int y) {
-        if (x < y) {
-            foo(y, x);
+    #define TO_ADD (123)
+
+    // This function will always recurse indefinitely and is only used to show
+    // coding style
+    int foo_function(int x, int some_value) {
+        if (x < some_value) {
+            foo(some_value, x);
         } else {
-            foo(x + 1, y - 1);
+            foo(x + TO_ADD, some_value - 1);
         }
 
-        for (int i = 0; i < x; i++) {
+        for (int my_counter = 0; my_counter < x; my_counter++) {
         }
     }
 

CONTRIBUTING.md

@@ -0,0 +1,8 @@
+When reporting an issue and especially submitting a pull request, please
+make sure that you are acquainted with Contributor Guidelines:
+
+https://github.com/micropython/micropython/wiki/ContributorGuidelines
+
+and Code Conventions:
+
+https://github.com/micropython/micropython/blob/master/CODECONVENTIONS.md

LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2013 Damien P. George
+Copyright (c) 2013, 2014 Damien P. George
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

README.md

@@ -1,41 +1,61 @@
-[![Build Status][travis-img]][travis-repo]
+[![Build Status][travis-img]][travis-repo] [![Coverage Status][coveralls-img]][coveralls-repo] [![Issue Stats][istats-pr-img]][istats-pr-repo] [![Issue Stats][istats-issue-img]][istats-issue-repo]
 [travis-img]:  https://travis-ci.org/micropython/micropython.png?branch=master
 [travis-repo]: https://travis-ci.org/micropython/micropython
+[coveralls-img]:  https://coveralls.io/repos/micropython/micropython/badge.png?branch=master
+[coveralls-repo]: https://coveralls.io/r/micropython/micropython?branch=master
+[istats-pr-img]: http://issuestats.com/github/micropython/micropython/badge/pr
+[istats-pr-repo]: http://issuestats.com/github/micropython/micropython
+[istats-issue-img]: http://issuestats.com/github/micropython/micropython/badge/issue
+[istats-issue-repo]: http://issuestats.com/github/micropython/micropython
 
-The Micro Python project
-========================
+The MicroPython project
+=======================
 <p align="center">
-  <img src="https://raw2.github.com/micropython/micropython/master/logo/upython-with-micro.jpg" alt="MicroPython Logo"/>
+  <img src="https://raw.githubusercontent.com/micropython/micropython/master/logo/upython-with-micro.jpg" alt="MicroPython Logo"/>
 </p>
 
-This is the Micro Python project, which aims to put an implementation
-of Python 3.x on a microcontroller.
+This is the MicroPython project, which aims to put an implementation
+of Python 3.x on microcontrollers and small embedded systems.
+You can find the official website at [micropython.org](http://www.micropython.org).
 
-WARNING: this project is in its early stages and is subject to large
-changes of the code-base, including project-wide name changes and API
-changes.
+WARNING: this project is in beta stage and is subject to changes of the
+code-base, including project-wide name changes and API changes.
+
+MicroPython implements the entire Python 3.4 syntax (including exceptions,
+"with", "yield from", etc., and additionally "async" keyword from Python 3.5).
+The following core datatypes are provided: str (including basic Unicode
+support), bytes, bytearray, tuple, list, dict, set, frozenset, array.array,
+collections.namedtuple, classes and instances. Builtin modules include sys,
+time, and struct.  Note that only subset of Python 3.4 functionality
+implemented for the data types and modules.
 
 See the repository www.github.com/micropython/pyboard for the Micro
-Python board.
+Python board, the officially supported reference electronic circuit board.
 
 Major components in this repository:
-- py/ -- the core Python implementation, including compiler and runtime.
-- unix/ -- a version of Micro Python that runs on Unix.
-- stmhal/ -- a version of Micro Python that runs on the Micro Python board
-  with an STM32F405RG (using ST's new Cube HAL drivers).
-- teensy/ -- a version of Micro Python that runs on the Teensy 3.1
-  (preliminary but functional).
+- py/ -- the core Python implementation, including compiler, runtime, and
+  core library.
+- unix/ -- a version of MicroPython that runs on Unix.
+- stmhal/ -- a version of MicroPython that runs on the MicroPython board
+  with an STM32F405RG (using ST's Cube HAL drivers).
+- minimal/ -- a minimal MicroPython port. Start with this if you want
+  to port MicroPython to another microcontroller.
+- tests/ -- test framework and test scripts.
+- docs/ -- user documentation in Sphinx reStructuredText format.
 
 Additional components:
-- bare-arm/ -- a bare minimum version of Micro Python for ARM MCUs.  Start
-  with this if you want to port Micro Python to another microcontroller.
-- stm/ -- obsolete version of Micro Python for the Micro Python board
-  that uses ST's old peripheral drivers.
-- unix-cpy/ -- a version of Micro Python that outputs bytecode (for testing).
-- tests/ -- test framework and test scripts.
+- bare-arm/ -- a bare minimum version of MicroPython for ARM MCUs. Used
+  mostly to control code size.
+- teensy/ -- a version of MicroPython that runs on the Teensy 3.1
+  (preliminary but functional).
+- pic16bit/ -- a version of MicroPython for 16-bit PIC microcontrollers.
+- cc3200/ -- a version of MicroPython that runs on the CC3200 from TI.
+- esp8266/ -- an experimental port for ESP8266 WiFi modules.
 - tools/ -- various tools, including the pyboard.py module.
 - examples/ -- a few example Python scripts.
 
+The subdirectories above may include READMEs with additional info.
+
 "make" is used to build the components, or "gmake" on BSD-based systems.
 You will also need bash and Python (at least 2.7 or 3.3).
 
@@ -44,30 +64,77 @@ The Unix version
 
 The "unix" port requires a standard Unix environment with gcc and GNU make.
 x86 and x64 architectures are supported (i.e. x86 32- and 64-bit), as well
-as ARMv7. Porting to other architectures require writing some assembly code
-for the exception handling.
+as ARM and MIPS. Making full-featured port to another architecture requires
+writing some assembly code for the exception handling and garbage collection.
+Alternatively, fallback implementation based on setjmp/longjmp can be used.
 
-To build:
+To build (see section below for required dependencies):
 
     $ cd unix
+    $ make axtls
     $ make
 
-Then to test it:
+Then to give it a try:
 
     $ ./micropython
     >>> list(5 * x + y for x in range(10) for y in [4, 2, 1])
 
-Debian/Ubuntu/Mint derivative Linux distros will require build-essentials and
-libreadline-dev packages installed. To build FFI (Foreign Function Interface)
-module, libffi-dev package is required. If you have problems with some
-dependencies, they can be disabled in unix/mpconfigport.mk .
+Use `CTRL-D` (i.e. EOF) to exit the shell.
+Learn about command-line options (in particular, how to increase heap size
+which may be needed for larger applications):
+
+    $ ./micropython --help
+
+Run complete testsuite:
+
+    $ make test
+
+Unix version comes with a builtin package manager called upip, e.g.:
+
+    $ ./micropython -m upip install micropython-pystone
+    $ ./micropython -m pystone
+
+Browse available modules on
+[PyPI](https://pypi.python.org/pypi?%3Aaction=search&term=micropython).
+Standard library modules come from
+[micropython-lib](https://github.com/micropython/micropython-lib) project.
+
+External dependencies
+---------------------
+
+Building Unix version requires some dependencies installed. For
+Debian/Ubuntu/Mint derivative Linux distros, install `build-essential`
+(includes toolchain and make), `libffi-dev`, and `pkg-config` packages.
+
+Other dependencies can be built together with MicroPython. Oftentimes,
+you need to do this to enable extra features or capabilities. To build
+these additional dependencies, first fetch git submodules for them:
+
+    $ git submodule update --init
+
+Use this same command to get the latest versions of dependencies, as
+they are updated from time to time. After that, in `unix/` dir, execute:
+
+    $ make deplibs
+
+This will build all available dependencies (regardless whether they
+are used or not). If you intend to build MicroPython with additional
+options (like cross-compiling), the same set of options should be passed
+to `make deplibs`. To actually enabled use of dependencies, edit
+`unix/mpconfigport.mk` file, which has inline descriptions of the options.
+For example, to build SSL module (required for `upip` tool described above),
+set `MICROPY_PY_USSL` to 1.
+
+In `unix/mpconfigport.mk`, you can also disable some dependencies enabled
+by default, like FFI support, which requires libffi development files to
+be installed.
 
 The STM version
 ---------------
 
 The "stmhal" port requires an ARM compiler, arm-none-eabi-gcc, and associated
 bin-utils.  For those using Arch Linux, you need arm-none-eabi-binutils and
-arm-none-eabi-gcc packages from the AUR.  Otherwise, try here:
+arm-none-eabi-gcc packages.  Otherwise, try here:
 https://launchpad.net/gcc-arm-embedded
 
 To build:
@@ -81,6 +148,9 @@ on the bottom left of the board, second row from the bottom).
 
 Then to flash the code via USB DFU to your device:
 
-    $ dfu-util -a 0 -D build/flash.dfu
+    $ make deploy
 
-You will need the dfu-util program, on Arch Linux it's dfu-util-git in the AUR.
+This will use the included `tools/pydfu.py` script.  If flashing the firmware
+does not work it may be because you don't have the correct permissions, and
+need to use `sudo make deploy`.
+See the README.md file in the stmhal/ directory for further details.

bare-arm/Makefile

@@ -8,12 +8,12 @@ include ../py/py.mk
 
 CROSS_COMPILE = arm-none-eabi-
 
-INC =  -I.
-INC += -I$(PY_SRC)
+INC += -I.
+INC += -I..
 INC += -I$(BUILD)
 
 CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion
-CFLAGS = $(INC) -Wall -Werror -ansi -std=gnu99 $(CFLAGS_CORTEX_M4) $(COPT)
+CFLAGS = $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_CORTEX_M4) $(COPT)
 
 #Debugging/Optimization
 ifeq ($(DEBUG), 1)
@@ -22,7 +22,7 @@ else
 CFLAGS += -Os -DNDEBUG
 endif
 
-LDFLAGS = --nostdlib -T stm32f405.ld
+LDFLAGS = -nostdlib -T stm32f405.ld -Map=$@.map --cref
 LIBS =
 
 SRC_C = \
@@ -38,11 +38,11 @@ SRC_S = \
 
 OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o))
 
-all: $(BUILD)/flash.elf
+all: $(BUILD)/firmware.elf
 
-$(BUILD)/flash.elf: $(OBJ)
+$(BUILD)/firmware.elf: $(OBJ)
 	$(ECHO) "LINK $@"
-	$(Q)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
+	$(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
 	$(Q)$(SIZE) $@
 
 include ../py/mkrules.mk

bare-arm/main.c

@@ -2,67 +2,38 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "mpconfig.h"
-#include "nlr.h"
-#include "misc.h"
-#include "qstr.h"
-#include "lexer.h"
-#include "parse.h"
-#include "obj.h"
-#include "parsehelper.h"
-#include "compile.h"
-#include "runtime0.h"
-#include "runtime.h"
-#include "repl.h"
+#include "py/nlr.h"
+#include "py/compile.h"
+#include "py/runtime.h"
+#include "py/repl.h"
 
-void do_str(const char *src) {
+void do_str(const char *src, mp_parse_input_kind_t input_kind) {
     mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0);
     if (lex == NULL) {
         return;
     }
 
-    mp_parse_error_kind_t parse_error_kind;
-    mp_parse_node_t pn = mp_parse(lex, MP_PARSE_SINGLE_INPUT, &parse_error_kind);
-
-    if (pn == MP_PARSE_NODE_NULL) {
-        // parse error
-        mp_parse_show_exception(lex, parse_error_kind);
-        mp_lexer_free(lex);
-        return;
-    }
-
-    // parse okay
-    qstr source_name = mp_lexer_source_name(lex);
-    mp_lexer_free(lex);
-    mp_obj_t module_fun = mp_compile(pn, source_name, MP_EMIT_OPT_NONE, true);
-    mp_parse_node_free(pn);
-
-    if (module_fun == mp_const_none) {
-        // compile error
-        return;
-    }
-
     nlr_buf_t nlr;
     if (nlr_push(&nlr) == 0) {
+        qstr source_name = lex->source_name;
+        mp_parse_tree_t parse_tree = mp_parse(lex, input_kind);
+        mp_obj_t module_fun = mp_compile(&parse_tree, source_name, MP_EMIT_OPT_NONE, true);
         mp_call_function_0(module_fun);
         nlr_pop();
     } else {
         // uncaught exception
-        mp_obj_print_exception((mp_obj_t)nlr.ret_val);
+        mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val);
     }
 }
 
 int main(int argc, char **argv) {
-    qstr_init();
     mp_init();
-    do_str("print('hello world!', list(x+1 for x in range(10)), end='eol\n')");
+    do_str("print('hello world!', list(x+1 for x in range(10)), end='eol\\n')", MP_PARSE_SINGLE_INPUT);
+    do_str("for i in range(10):\n  print(i)", MP_PARSE_FILE_INPUT);
     mp_deinit();
     return 0;
 }
 
-void gc_collect(void) {
-}
-
 mp_lexer_t *mp_lexer_new_from_file(const char *filename) {
     return NULL;
 }
@@ -71,14 +42,25 @@ mp_import_stat_t mp_import_stat(const char *path) {
     return MP_IMPORT_STAT_NO_EXIST;
 }
 
-mp_obj_t mp_builtin_open(uint n_args, const mp_obj_t *args) {
+mp_obj_t mp_builtin_open(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) {
     return mp_const_none;
 }
-MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_open_obj, 1, 2, mp_builtin_open);
+MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open);
 
 void nlr_jump_fail(void *val) {
 }
 
+void NORETURN __fatal_error(const char *msg) {
+    while (1);
+}
+
+#ifndef NDEBUG
+void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) {
+    printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line);
+    __fatal_error("Assertion failed");
+}
+#endif
+
 /*
 int _lseek() {return 0;}
 int _read() {return 0;}

bare-arm/mpconfigport.h

@@ -2,41 +2,68 @@
 
 // options to control how Micro Python is built
 
+#define MICROPY_QSTR_BYTES_IN_HASH  (1)
+#define MICROPY_ALLOC_PATH_MAX      (512)
 #define MICROPY_EMIT_X64            (0)
 #define MICROPY_EMIT_THUMB          (0)
 #define MICROPY_EMIT_INLINE_THUMB   (0)
+#define MICROPY_COMP_MODULE_CONST   (0)
+#define MICROPY_COMP_CONST          (0)
+#define MICROPY_COMP_DOUBLE_TUPLE_ASSIGN (0)
+#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (0)
 #define MICROPY_MEM_STATS           (0)
 #define MICROPY_DEBUG_PRINTERS      (0)
 #define MICROPY_ENABLE_GC           (0)
-#define MICROPY_ENABLE_REPL_HELPERS (0)
-#define MICROPY_ENABLE_LEXER_UNIX   (0)
+#define MICROPY_HELPER_REPL         (0)
+#define MICROPY_HELPER_LEXER_UNIX   (0)
 #define MICROPY_ENABLE_SOURCE_LINE  (0)
-#define MICROPY_ENABLE_MOD_COLLECTIONS (0)
-#define MICROPY_ENABLE_MOD_MATH     (0)
-#define MICROPY_ENABLE_MOD_CMATH    (0)
-#define MICROPY_ENABLE_MOD_IO       (0)
-#define MICROPY_ENABLE_MOD_STRUCT   (0)
-#define MICROPY_ENABLE_MOD_SYS      (0)
-#define MICROPY_ENABLE_PROPERTY     (0)
+#define MICROPY_ENABLE_DOC_STRING   (0)
+#define MICROPY_ERROR_REPORTING     (MICROPY_ERROR_REPORTING_TERSE)
+#define MICROPY_BUILTIN_METHOD_CHECK_SELF_ARG (0)
+#define MICROPY_PY_ASYNC_AWAIT (0)
+#define MICROPY_PY_BUILTINS_BYTEARRAY (0)
+#define MICROPY_PY_BUILTINS_MEMORYVIEW (0)
+#define MICROPY_PY_BUILTINS_ENUMERATE (0)
+#define MICROPY_PY_BUILTINS_FROZENSET (0)
+#define MICROPY_PY_BUILTINS_REVERSED (0)
+#define MICROPY_PY_BUILTINS_SET     (0)
+#define MICROPY_PY_BUILTINS_SLICE   (0)
+#define MICROPY_PY_BUILTINS_PROPERTY (0)
+#define MICROPY_PY___FILE__         (0)
+#define MICROPY_PY_GC               (0)
+#define MICROPY_PY_ARRAY            (0)
+#define MICROPY_PY_ATTRTUPLE        (0)
+#define MICROPY_PY_COLLECTIONS      (0)
+#define MICROPY_PY_MATH             (0)
+#define MICROPY_PY_CMATH            (0)
+#define MICROPY_PY_IO               (0)
+#define MICROPY_PY_STRUCT           (0)
+#define MICROPY_PY_SYS              (0)
 #define MICROPY_CPYTHON_COMPAT      (0)
 #define MICROPY_LONGINT_IMPL        (MICROPY_LONGINT_IMPL_NONE)
 #define MICROPY_FLOAT_IMPL          (MICROPY_FLOAT_IMPL_NONE)
-#define MICROPY_PATH_MAX            (512)
+#define MICROPY_USE_INTERNAL_PRINTF (0)
 
 // type definitions for the specific machine
 
 #define BYTES_PER_WORD (4)
 
+#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1))
+
 #define UINT_FMT "%lu"
 #define INT_FMT "%ld"
 
-typedef int32_t machine_int_t; // must be pointer size
-typedef uint32_t machine_uint_t; // must be pointer size
-typedef void *machine_ptr_t; // must be of pointer size
-typedef const void *machine_const_ptr_t; // must be of pointer size
+typedef int32_t mp_int_t; // must be pointer size
+typedef uint32_t mp_uint_t; // must be pointer size
+typedef long mp_off_t;
+
+// dummy print
+#define MP_PLAT_PRINT_STRN(str, len) (void)0
 
 // extra built in names to add to the global namespace
-extern const struct _mp_obj_fun_native_t mp_builtin_open_obj;
-#define MICROPY_EXTRA_BUILTINS \
+extern const struct _mp_obj_fun_builtin_t mp_builtin_open_obj;
+#define MICROPY_PORT_BUILTINS \
     { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj },
 
+// We need to provide a declaration/definition of alloca()
+#include <alloca.h>

bare-arm/mphalport.h

@@ -0,0 +1 @@
+// empty file

cc3200/FreeRTOS/FreeRTOSConfig.h

@@ -0,0 +1,173 @@
+/*
+    FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION			        1
+#define configUSE_IDLE_HOOK                     1
+#define configUSE_TICK_HOOK				        1
+#define configCPU_CLOCK_HZ				        ( ( unsigned long ) 80000000 )
+#define configTICK_RATE_HZ				        ( ( TickType_t ) 1000 )
+#define configMINIMAL_STACK_SIZE		        ( ( unsigned short ) 72 )
+#define configTOTAL_HEAP_SIZE			        ( ( size_t ) ( \
+    16384 /* 16kbytes for FreeRTOS data structures and heap */ \
+    - sizeof(StaticTask_t) - configMINIMAL_STACK_SIZE * sizeof(StackType_t) /* TCB+stack for idle task */ \
+    - sizeof(StaticTask_t) - 1024 /* TCB+stack for servers task */ \
+    - sizeof(StaticTask_t) - 6656 /* TCB+stack for main MicroPython task */ \
+    - sizeof(StaticTask_t) - 896 /* TCB+stack for simplelink spawn task */ \
+    ) )
+#define configMAX_TASK_NAME_LEN			        ( 8 )
+#define configUSE_TRACE_FACILITY		        0
+#define configUSE_16_BIT_TICKS			        0
+#define configIDLE_SHOULD_YIELD			        1
+#define configUSE_CO_ROUTINES 			        0
+#define configUSE_MUTEXES				        0
+#define configUSE_RECURSIVE_MUTEXES		        0
+#ifdef DEBUG
+#define configCHECK_FOR_STACK_OVERFLOW	        1
+#else
+#define configCHECK_FOR_STACK_OVERFLOW          0
+#endif
+#define configUSE_QUEUE_SETS			        0
+#define configUSE_COUNTING_SEMAPHORES	        0
+#define configUSE_ALTERNATIVE_API		        0
+
+#define configMAX_PRIORITIES			        ( 4UL )
+#define configMAX_CO_ROUTINE_PRIORITIES         ( 2 )
+#define configQUEUE_REGISTRY_SIZE		        0
+
+/* Timer related defines. */
+#define configUSE_TIMERS				        0
+#define configTIMER_TASK_PRIORITY		        2
+#define configTIMER_QUEUE_LENGTH		        20
+#define configTIMER_TASK_STACK_DEPTH	        ( configMINIMAL_STACK_SIZE * 2 )
+#ifdef DEBUG
+#define configUSE_MALLOC_FAILED_HOOK            1
+#else
+#define configUSE_MALLOC_FAILED_HOOK            0
+#endif
+#define configENABLE_BACKWARD_COMPATIBILITY     0
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet				0
+#define INCLUDE_uxTaskPriorityGet				0
+#define INCLUDE_vTaskDelete						0
+#define INCLUDE_vTaskCleanUpResources			0
+#define INCLUDE_vTaskSuspend					0
+#define INCLUDE_vTaskDelayUntil					0
+#define INCLUDE_vTaskDelay						1
+#ifdef DEBUG
+#define INCLUDE_uxTaskGetStackHighWaterMark		1
+#else
+#define INCLUDE_uxTaskGetStackHighWaterMark     0
+#endif
+#define INCLUDE_xTaskGetSchedulerState			0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle	0
+#ifdef DEBUG
+#define INCLUDE_xTaskGetIdleTaskHandle			1
+#else
+#define INCLUDE_xTaskGetIdleTaskHandle          0
+#endif
+#define INCLUDE_pcTaskGetTaskName				0
+#define INCLUDE_eTaskGetState					0
+#define INCLUDE_xSemaphoreGetMutexHolder		0
+
+#define configKERNEL_INTERRUPT_PRIORITY 		( 7 << 5 )	/* Priority 7, or 255 as only the top three bits are implemented.  This is the lowest priority. */
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( 1 << 5 )  /* Priority 5, or 160 as only the top three bits are implemented. */
+
+/* Use the Cortex-M3 optimised task selection rather than the generic C code
+version. */
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* We provide a definition of ucHeap so it can go in a special segment. */
+#define configAPPLICATION_ALLOCATED_HEAP 1
+
+/* We use static versions of functions (like xTaskCreateStatic) */
+#define configSUPPORT_STATIC_ALLOCATION 1
+
+/* For threading */
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 1
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+#undef INCLUDE_vTaskDelete
+#define INCLUDE_vTaskDelete 1
+
+#endif /* FREERTOS_CONFIG_H */

cc3200/FreeRTOS/License/license.txt

@@ -0,0 +1,399 @@
+The FreeRTOS open source license covers the FreeRTOS source files,
+which are located in the /FreeRTOS/Source directory of the official FreeRTOS
+download.  It also covers most of the source files in the demo application
+projects, which are located in the /FreeRTOS/Demo directory of the official
+FreeRTOS download.  The demo projects may also include third party software that
+is not part of FreeRTOS and is licensed separately to FreeRTOS.  Examples of
+third party software includes header files provided by chip or tools vendors,
+linker scripts, peripheral drivers, etc.  All the software in subdirectories of
+the /FreeRTOS directory is either open source or distributed with permission,
+and is free for use.  For the avoidance of doubt, refer to the comments at the
+top of each source file.
+
+----------------------------------------------------------------------------
+
+NOTE: The modification to the GPL is included to allow you to distribute a
+combined work that includes FreeRTOS without being obliged to provide the source
+code for proprietary components.
+
+----------------------------------------------------------------------------
+
+Applying to FreeRTOS V8.2.3 up to the latest version, the FreeRTOS GPL Exception
+Text follows:
+
+Any FreeRTOS *source code*, whether modified or in it's original release form,
+or whether in whole or in part, can only be distributed by you under the terms
+of the GNU General Public License plus this exception.  An independent module is
+a module which is not derived from or based on FreeRTOS.
+
+Clause 1:
+
+Linking FreeRTOS with other modules is making a combined work based on FreeRTOS.
+Thus, the terms and conditions of the GNU General Public License V2 cover the
+whole combination.
+
+As a special exception, the copyright holders of FreeRTOS give you permission to
+link FreeRTOS with independent modules to produce a statically linked
+executable, regardless of the license terms of these independent modules, and to
+copy and distribute the resulting executable under terms of your choice,
+provided that you also meet, for each linked independent module, the terms and
+conditions of the license of that module.  An independent module is a module
+which is not derived from or based on FreeRTOS.
+
+Clause 2:
+
+FreeRTOS may not be used for any competitive or comparative purpose, including
+the publication of any form of run time or compile time metric, without the
+express permission of Real Time Engineers Ltd. (this is the norm within the
+industry and is intended to ensure information accuracy).
+
+
+
+--------------------------------------------------------------------
+
+
+
+The standard GPL V2 text:
+
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary.  To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License.  The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language.  (Hereinafter, translation is included without limitation in
+the term "modification".)  Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope.  The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices
+    stating that you changed the files and the date of any change.
+
+    b) You must cause any work that you distribute or publish, that in
+    whole or in part contains or is derived from the Program or any
+    part thereof, to be licensed as a whole at no charge to all third
+    parties under the terms of this License.
+
+    c) If the modified program normally reads commands interactively
+    when run, you must cause it, when started running for such
+    interactive use in the most ordinary way, to print or display an
+    announcement including an appropriate copyright notice and a
+    notice that there is no warranty (or else, saying that you provide
+    a warranty) and that users may redistribute the program under
+    these conditions, and telling the user how to view a copy of this
+    License.  (Exception: if the Program itself is interactive but
+    does not normally print such an announcement, your work based on
+    the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works.  But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+  3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+    a) Accompany it with the complete corresponding machine-readable
+    source code, which must be distributed under the terms of Sections
+    1 and 2 above on a medium customarily used for software interchange; or,
+
+    b) Accompany it with a written offer, valid for at least three
+    years, to give any third party, for a charge no more than your
+    cost of physically performing source distribution, a complete
+    machine-readable copy of the corresponding source code, to be
+    distributed under the terms of Sections 1 and 2 above on a medium
+    customarily used for software interchange; or,
+
+    c) Accompany it with the information you received as to the offer
+    to distribute corresponding source code.  (This alternative is
+    allowed only for noncommercial distribution and only if you
+    received the program in object code or executable form with such
+    an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it.  For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable.  However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not
+signed it.  However, nothing else grants you permission to modify or
+distribute the Program or its derivative works.  These actions are
+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions.  You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all.  For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License** as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) year name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
+

cc3200/FreeRTOS/Source/croutine.c

@@ -0,0 +1,395 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
+static List_t xDelayedCoRoutineList1;									/*< Delayed co-routines. */
+static List_t xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static List_t * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
+static List_t * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static List_t xPendingReadyCoRoutineList;								/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+CRCB_t * pxCurrentCoRoutine = NULL;
+static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE	( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
+{																													\
+	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
+	{																												\
+		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
+	}																												\
+	vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
+}
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
+{
+BaseType_t xReturn;
+CRCB_t *pxCoRoutine;
+
+	/* Allocate the memory that will store the co-routine control block. */
+	pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+	if( pxCoRoutine )
+	{
+		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+		be created and the co-routine data structures need initialising. */
+		if( pxCurrentCoRoutine == NULL )
+		{
+			pxCurrentCoRoutine = pxCoRoutine;
+			prvInitialiseCoRoutineLists();
+		}
+
+		/* Check the priority is within limits. */
+		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+		{
+			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+		}
+
+		/* Fill out the co-routine control block from the function parameters. */
+		pxCoRoutine->uxState = corINITIAL_STATE;
+		pxCoRoutine->uxPriority = uxPriority;
+		pxCoRoutine->uxIndex = uxIndex;
+		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+		/* Initialise all the other co-routine control block parameters. */
+		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+		/* Set the co-routine control block as a link back from the ListItem_t.
+		This is so we can get back to the containing CRCB from a generic item
+		in a list. */
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+		/* Event lists are always in priority order. */
+		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+		/* Now the co-routine has been initialised it can be added to the ready
+		list at the correct priority. */
+		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
+{
+TickType_t xTimeToWake;
+
+	/* Calculate the time to wake - this may overflow but this is
+	not a problem. */
+	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+	/* We must remove ourselves from the ready list before adding
+	ourselves to the blocked list as the same list item is used for
+	both lists. */
+	( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+	/* The list item will be inserted in wake time order. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+	if( xTimeToWake < xCoRoutineTickCount )
+	{
+		/* Wake time has overflowed.  Place this item in the
+		overflow list. */
+		vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+	else
+	{
+		/* The wake time has not overflowed, so we can use the
+		current block list. */
+		vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+
+	if( pxEventList )
+	{
+		/* Also add the co-routine to an event list.  If this is done then the
+		function must be called with interrupts disabled. */
+		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckPendingReadyList( void )
+{
+	/* Are there any co-routines waiting to get moved to the ready list?  These
+	are co-routines that have been readied by an ISR.  The ISR cannot access
+	the	ready lists itself. */
+	while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+	{
+		CRCB_t *pxUnblockedCRCB;
+
+		/* The pending ready list can be accessed by an ISR. */
+		portDISABLE_INTERRUPTS();
+		{
+			pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
+			( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+		}
+		portENABLE_INTERRUPTS();
+
+		( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckDelayedList( void )
+{
+CRCB_t *pxCRCB;
+
+	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+	while( xPassedTicks )
+	{
+		xCoRoutineTickCount++;
+		xPassedTicks--;
+
+		/* If the tick count has overflowed we need to swap the ready lists. */
+		if( xCoRoutineTickCount == 0 )
+		{
+			List_t * pxTemp;
+
+			/* Tick count has overflowed so we need to swap the delay lists.  If there are
+			any items in pxDelayedCoRoutineList here then there is an error! */
+			pxTemp = pxDelayedCoRoutineList;
+			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+			pxOverflowDelayedCoRoutineList = pxTemp;
+		}
+
+		/* See if this tick has made a timeout expire. */
+		while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+		{
+			pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+			{
+				/* Timeout not yet expired. */
+				break;
+			}
+
+			portDISABLE_INTERRUPTS();
+			{
+				/* The event could have occurred just before this critical
+				section.  If this is the case then the generic list item will
+				have been moved to the pending ready list and the following
+				line is still valid.  Also the pvContainer parameter will have
+				been set to NULL so the following lines are also valid. */
+				( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+				/* Is the co-routine waiting on an event also? */
+				if( pxCRCB->xEventListItem.pvContainer )
+				{
+					( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+				}
+			}
+			portENABLE_INTERRUPTS();
+
+			prvAddCoRoutineToReadyQueue( pxCRCB );
+		}
+	}
+
+	xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+	/* See if any co-routines readied by events need moving to the ready lists. */
+	prvCheckPendingReadyList();
+
+	/* See if any delayed co-routines have timed out. */
+	prvCheckDelayedList();
+
+	/* Find the highest priority queue that contains ready co-routines. */
+	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+	{
+		if( uxTopCoRoutineReadyPriority == 0 )
+		{
+			/* No more co-routines to check. */
+			return;
+		}
+		--uxTopCoRoutineReadyPriority;
+	}
+
+	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+	 of the	same priority get an equal share of the processor time. */
+	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+	/* Call the co-routine. */
+	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+	vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+	/* Start with pxDelayedCoRoutineList using list1 and the
+	pxOverflowDelayedCoRoutineList using list2. */
+	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
+{
+CRCB_t *pxUnblockedCRCB;
+BaseType_t xReturn;
+
+	/* This function is called from within an interrupt.  It can only access
+	event lists and the pending ready list.  This function assumes that a
+	check has already been made to ensure pxEventList is not empty. */
+	pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+	vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+
+#endif /* configUSE_CO_ROUTINES == 0 */
+

cc3200/FreeRTOS/Source/event_groups.c

@@ -0,0 +1,752 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* The following bit fields convey control information in a task's event list
+item value.  It is important they don't clash with the
+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x0100U
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x0200U
+	#define eventWAIT_FOR_ALL_BITS			0x0400U
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff00U
+#else
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x01000000UL
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x02000000UL
+	#define eventWAIT_FOR_ALL_BITS			0x04000000UL
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff000000UL
+#endif
+
+typedef struct xEventGroupDefinition
+{
+	EventBits_t uxEventBits;
+	List_t xTasksWaitingForBits;		/*< List of tasks waiting for a bit to be set. */
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxEventGroupNumber;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* A StaticEventGroup_t object must be provided. */
+		configASSERT( pxEventGroupBuffer );
+
+		/* The user has provided a statically allocated event group - use it. */
+		pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note that
+				this event group was created statically in case the event group
+				is later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return ( EventGroupHandle_t ) pxEventBits;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreate( void )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* Allocate the event group. */
+		pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note this
+				event group was allocated statically in case the event group is
+				later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return ( EventGroupHandle_t ) pxEventBits;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+{
+EventBits_t uxOriginalBitValue, uxReturn;
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+BaseType_t xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		uxOriginalBitValue = pxEventBits->uxEventBits;
+
+		( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+		if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			/* All the rendezvous bits are now set - no need to block. */
+			uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+			/* Rendezvous always clear the bits.  They will have been cleared
+			already unless this is the only task in the rendezvous. */
+			pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+			xTicksToWait = 0;
+		}
+		else
+		{
+			if( xTicksToWait != ( TickType_t ) 0 )
+			{
+				traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+				/* Store the bits that the calling task is waiting for in the
+				task's event list item so the kernel knows when a match is
+				found.  Then enter the blocked state. */
+				vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+				/* This assignment is obsolete as uxReturn will get set after
+				the task unblocks, but some compilers mistakenly generate a
+				warning about uxReturn being returned without being set if the
+				assignment is omitted. */
+				uxReturn = 0;
+			}
+			else
+			{
+				/* The rendezvous bits were not set, but no block time was
+				specified - just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+			}
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			/* The task timed out, just return the current event bit value. */
+			taskENTER_CRITICAL();
+			{
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* Although the task got here because it timed out before the
+				bits it was waiting for were set, it is possible that since it
+				unblocked another task has set the bits.  If this is the case
+				then it needs to clear the bits before exiting. */
+				if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+				{
+					pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* Control bits might be set as the task had blocked should not be
+		returned. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+
+	traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+{
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventBits_t uxReturn, uxControlBits = 0;
+BaseType_t xWaitConditionMet, xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	/* Check the user is not attempting to wait on the bits used by the kernel
+	itself, and that at least one bit is being requested. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+		/* Check to see if the wait condition is already met or not. */
+		xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+		if( xWaitConditionMet != pdFALSE )
+		{
+			/* The wait condition has already been met so there is no need to
+			block. */
+			uxReturn = uxCurrentEventBits;
+			xTicksToWait = ( TickType_t ) 0;
+
+			/* Clear the wait bits if requested to do so. */
+			if( xClearOnExit != pdFALSE )
+			{
+				pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else if( xTicksToWait == ( TickType_t ) 0 )
+		{
+			/* The wait condition has not been met, but no block time was
+			specified, so just return the current value. */
+			uxReturn = uxCurrentEventBits;
+		}
+		else
+		{
+			/* The task is going to block to wait for its required bits to be
+			set.  uxControlBits are used to remember the specified behaviour of
+			this call to xEventGroupWaitBits() - for use when the event bits
+			unblock the task. */
+			if( xClearOnExit != pdFALSE )
+			{
+				uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( xWaitForAllBits != pdFALSE )
+			{
+				uxControlBits |= eventWAIT_FOR_ALL_BITS;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Store the bits that the calling task is waiting for in the
+			task's event list item so the kernel knows when a match is
+			found.  Then enter the blocked state. */
+			vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+			/* This is obsolete as it will get set after the task unblocks, but
+			some compilers mistakenly generate a warning about the variable
+			being returned without being set if it is not done. */
+			uxReturn = 0;
+
+			traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The task timed out, just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* It is possible that the event bits were updated between this
+				task leaving the Blocked state and running again. */
+				if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+				{
+					if( xClearOnExit != pdFALSE )
+					{
+						pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			/* Prevent compiler warnings when trace macros are not used. */
+			xTimeoutOccurred = pdFALSE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* The task blocked so control bits may have been set. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+	traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+{
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventBits_t uxReturn;
+
+	/* Check the user is not attempting to clear the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	taskENTER_CRITICAL();
+	{
+		traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+		/* The value returned is the event group value prior to the bits being
+		cleared. */
+		uxReturn = pxEventBits->uxEventBits;
+
+		/* Clear the bits. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+	{
+		BaseType_t xReturn;
+
+		traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+UBaseType_t uxSavedInterruptStatus;
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventBits_t uxReturn;
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		uxReturn = pxEventBits->uxEventBits;
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+{
+ListItem_t *pxListItem, *pxNext;
+ListItem_t const *pxListEnd;
+List_t *pxList;
+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+BaseType_t xMatchFound = pdFALSE;
+
+	/* Check the user is not attempting to set the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	pxList = &( pxEventBits->xTasksWaitingForBits );
+	pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+		pxListItem = listGET_HEAD_ENTRY( pxList );
+
+		/* Set the bits. */
+		pxEventBits->uxEventBits |= uxBitsToSet;
+
+		/* See if the new bit value should unblock any tasks. */
+		while( pxListItem != pxListEnd )
+		{
+			pxNext = listGET_NEXT( pxListItem );
+			uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+			xMatchFound = pdFALSE;
+
+			/* Split the bits waited for from the control bits. */
+			uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+			uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+			if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+			{
+				/* Just looking for single bit being set. */
+				if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+				{
+					xMatchFound = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+			{
+				/* All bits are set. */
+				xMatchFound = pdTRUE;
+			}
+			else
+			{
+				/* Need all bits to be set, but not all the bits were set. */
+			}
+
+			if( xMatchFound != pdFALSE )
+			{
+				/* The bits match.  Should the bits be cleared on exit? */
+				if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+				{
+					uxBitsToClear |= uxBitsWaitedFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Store the actual event flag value in the task's event list
+				item before removing the task from the event list.  The
+				eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+				that is was unblocked due to its required bits matching, rather
+				than because it timed out. */
+				( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+			}
+
+			/* Move onto the next list item.  Note pxListItem->pxNext is not
+			used here as the list item may have been removed from the event list
+			and inserted into the ready/pending reading list. */
+			pxListItem = pxNext;
+		}
+
+		/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+		bit was set in the control word. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	( void ) xTaskResumeAll();
+
+	return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_DELETE( xEventGroup );
+
+		while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+		{
+			/* Unblock the task, returning 0 as the event list is being deleted
+			and	cannot therefore have any bits set. */
+			configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+			( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+		}
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+		{
+			/* The event group can only have been allocated dynamically - free
+			it again. */
+			vPortFree( pxEventBits );
+		}
+		#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		{
+			/* The event group could have been allocated statically or
+			dynamically, so check before attempting to free the memory. */
+			if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+			{
+				vPortFree( pxEventBits );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+	( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+an interrupt. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
+{
+	( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+an interrupt. */
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
+{
+	( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
+{
+BaseType_t xWaitConditionMet = pdFALSE;
+
+	if( xWaitForAllBits == pdFALSE )
+	{
+		/* Task only has to wait for one bit within uxBitsToWaitFor to be
+		set.  Is one already set? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+		Are they set already? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	BaseType_t xReturn;
+
+		traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TRACE_FACILITY == 1)
+
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
+	{
+	UBaseType_t xReturn;
+	EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+
+		if( xEventGroup == NULL )
+		{
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = pxEventBits->uxEventGroupNumber;
+		}
+
+		return xReturn;
+	}
+
+#endif
+

cc3200/FreeRTOS/Source/include/StackMacros.h

@@ -0,0 +1,171 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+

cc3200/FreeRTOS/Source/include/croutine.h

@@ -0,0 +1,762 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block.  The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+	crCOROUTINE_CODE 	pxCoRoutineFunction;
+	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
+	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
+	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
+	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *<pre>
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );</pre>
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+   </pre>
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *<pre>
+ void vCoRoutineSchedule( void );</pre>
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+   <pre>
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+ </pre>
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * <pre>
+ crSTART( CoRoutineHandle_t xHandle );</pre>
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * <pre>
+ crEND();</pre>
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *<pre>
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )												\
+	if( ( xTicksToDelay ) > 0 )															\
+	{																					\
+		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
+	}																					\
+	crSET_STATE0( ( xHandle ) );
+
+/**
+ * <pre>
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
+	if( *( pxResult ) == errQUEUE_BLOCKED )												\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
+	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
+	}																					\
+	if( *( pxResult ) == errQUEUE_YIELD )												\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*( pxResult ) = pdPASS;															\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }</pre>
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */

cc3200/FreeRTOS/Source/include/deprecated_definitions.h

@@ -0,0 +1,321 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.  The
+definitions below remain in the code for backward compatibility only.  New
+projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+	#include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+	#include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+	#include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+	#include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+	#include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+   #ifdef __AVR32_AVR32A__
+	   #include "portmacro.h"
+   #endif
+#endif
+
+#ifdef __ICCAVR32__
+   #ifdef __CORE__
+      #if __CORE__ == __AVR32A__
+	      #include "portmacro.h"
+      #endif
+   #endif
+#endif
+
+#ifdef __91467D
+	#include "portmacro.h"
+#endif
+
+#ifdef __96340
+	#include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
+

cc3200/FreeRTOS/Source/include/event_groups.h

@@ -0,0 +1,797 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+typedef void * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreate( void );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+   <pre>
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+   </pre>
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+   </pre>
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+ </pre>
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ </pre>
+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ </pre>
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+ </pre>
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ <pre>
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+ </pre>
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if (configUSE_TRACE_FACILITY == 1)
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+

cc3200/FreeRTOS/Source/include/list.h

@@ -0,0 +1,453 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+#ifndef INC_FREERTOS_H
+	#error FreeRTOS.h must be included before list.h
+#endif
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+	#define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros that can be used to place known values within the list structures,
+then check that the known values do not get corrupted during the execution of
+the application.   These may catch the list data structures being overwritten in
+memory.  They will not catch data errors caused by incorrect configuration or
+use of FreeRTOS.*/
+#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+	/* Define the macros to do nothing. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+	#define listTEST_LIST_INTEGRITY( pxList )
+#else
+	/* Define macros that add new members into the list structures. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
+
+	/* Define macros that set the new structure members to known values. */
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+	/* Define macros that will assert if one of the structure members does not
+	contain its expected value. */
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
+	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+	void * configLIST_VOLATILE pvContainer;				/*< Pointer to the list in which this list item is placed (if any). */
+	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE UBaseType_t uxNumberOfItems;
+	ListItem_t * configLIST_VOLATILE pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+	MiniListItem_t xListEnd;							/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )	( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
+{																							\
+List_t * const pxConstList = ( pxList );													\
+	/* Increment the index to the next item and return the item, ensuring */				\
+	/* we don't return the marker used at the end of the list.  */							\
+	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
+	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
+	{																						\
+		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
+	}																						\
+	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

cc3200/FreeRTOS/Source/include/mpu_prototypes.h

@@ -0,0 +1,177 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API function. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
+void MPU_vTaskDelay( const TickType_t xTicksToDelay );
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
+UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
+void MPU_vTaskResume( TaskHandle_t xTaskToResume );
+void MPU_vTaskStartScheduler( void );
+void MPU_vTaskSuspendAll( void );
+BaseType_t MPU_xTaskResumeAll( void );
+TickType_t MPU_xTaskGetTickCount( void );
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
+void MPU_vTaskList( char * pcWriteBuffer );
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
+BaseType_t MPU_xTaskIncrementTick( void );
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+void MPU_vTaskMissedYield( void );
+BaseType_t MPU_xTaskGetSchedulerState( void );
+
+/* MPU versions of queue.h API function. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
+BaseType_t MPU_xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek );
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+void MPU_vQueueDelete( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
+void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
+
+/* MPU versions of timers.h API function. */
+TimerHandle_t MPU_xTimerCreate(	const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
+TimerHandle_t MPU_xTimerCreateStatic(	const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
+BaseType_t MPU_xTimerCreateTimerTask( void );
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
+
+/* MPU versions of event_group.h API function. */
+EventGroupHandle_t MPU_xEventGroupCreate( void );
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
+
+#endif /* MPU_PROTOTYPES_H */
+

cc3200/FreeRTOS/Source/include/mpu_wrappers.h

@@ -0,0 +1,201 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueGenericReceive					MPU_xQueueGenericReceive
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Remove the privileged function macro. */
+		#define PRIVILEGED_FUNCTION
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+

cc3200/FreeRTOS/Source/include/portable.h

@@ -0,0 +1,207 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+

cc3200/FreeRTOS/Source/include/projdefs.h

@@ -0,0 +1,161 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN	0
+#define pdFREERTOS_BIG_ENDIAN		1
+
+#endif /* PROJDEFS_H */
+
+
+

cc3200/FreeRTOS/Source/list.c

@@ -0,0 +1,240 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#include <stdlib.h>
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pvContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCB's which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see http://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		http://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   http://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pvContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+

cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

@@ -0,0 +1,710 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined.  The value should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	orr r14, #0xd					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r3, r14}				\n"
+	"	mov r0, %0							\n"
+	"	msr basepri, r0						\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r3, r14}				\n"
+	"										\n"	/* Restore the context, including the critical nesting count. */
+	"	ldr r1, [r3]						\n"
+	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Stop SysTick.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with respect to calendar time. */
+			ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
+			portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" );
+
+			if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt has already executed, and the SysTick
+				count reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value.  The critical section is used to ensure the tick interrupt
+			can only execute once in the case that the reload register is near
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portENTER_CRITICAL();
+			{
+				portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+				vTaskStepTick( ulCompleteTickPeriods );
+				portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+			}
+			portEXIT_CRITICAL();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredicable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h

@@ -0,0 +1,284 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" );													\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue )
+	);
+}
+/*-----------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c

@@ -0,0 +1,478 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+

cc3200/Makefile

@@ -0,0 +1,41 @@
+# Select the board to build for: if not given on the command line,
+# then default to WIPY
+BOARD ?= WIPY
+ifeq ($(wildcard boards/$(BOARD)/.),)
+$(error Invalid BOARD specified)
+endif
+
+# Make 'release' the default build type
+BTYPE ?= release
+
+# If the build directory is not given, make it reflect the board name.
+BUILD ?= build/$(BOARD)/$(BTYPE)
+
+include ../py/mkenv.mk
+-include ../../localconfig.mk
+
+CROSS_COMPILE ?= arm-none-eabi-
+
+CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -march=armv7e-m -mabi=aapcs -mcpu=cortex-m4 -msoft-float -mfloat-abi=soft -fsingle-precision-constant -Wdouble-promotion
+CFLAGS = -Wall -Wpointer-arith -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_CORTEX_M4) -Os
+CFLAGS += -g -ffunction-sections -fdata-sections -fno-common -fsigned-char -mno-unaligned-access
+CFLAGS += -Iboards/$(BOARD)
+
+LDFLAGS = -Wl,-nostdlib -Wl,--gc-sections -Wl,-Map=$@.map
+
+ifeq ($(BTARGET), application)
+# qstr definitions (must come before including py.mk)
+QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h
+# include MicroPython make definitions
+include ../py/py.mk
+include application.mk
+else
+ifeq ($(BTARGET), bootloader)
+include bootmgr/bootloader.mk
+else
+$(error Invalid BTARGET specified)
+endif
+endif
+
+# always include MicroPython make rules
+include ../py/mkrules.mk

cc3200/README.md

@@ -0,0 +1,93 @@
+# Build Instructions for the CC3200
+
+Currently the CC3200 port of MicroPython builds under Linux and OSX **but not under Windows**.
+
+The tool chain required for the build can be found at <https://launchpad.net/gcc-arm-embedded>.
+
+In order to download the image to the CC3200 you will need the CCS_Uniflash tool from TI, which at this 
+moment is only available for Windows, so, you need Linux/OSX to build and Windows to flash the image.
+
+## To build an image suitable for debugging:
+
+In order to debug the port specific code, optimizations need to be disabled on the 
+port file (check the Makefile for specific details). You can use CCS from TI.
+Use the CC3200.ccxml file supplied with this distribution for the debuuger configuration. 
+```bash
+make BTARGET=application BTYPE=debug BOARD=LAUNCHXL
+```
+## To build an image suitable to be flashed to the device:
+```bash
+make BTARGET=application BTYPE=release BOARD=LAUNCHXL
+```
+## Building the bootloader
+```bash
+make BTARGET=bootloader BTYPE=release BOARD=LAUNCHXL
+```
+
+## Regarding old revisions of the CC3200-LAUNCHXL
+First silicon (pre-release) revisions of the CC3200 had issues with the ram blocks, and MicroPython cannot run
+there. Make sure to use a **v4.1 (or higer) LAUNCHXL board** when trying this port, otherwise it won't work.
+
+## Flashing the CC3200
+- Make sure that you have built both the *bootloader* and the *application* in **release** mode.
+- Make sure the SOP2 jumper is in position.
+- Open CCS_Uniflash and connect to the board (by default on port 22). 
+- Format the serial flash (select 1MB size in case of the CC3200-LAUNCHXL, 2MB in case of the WiPy, leave the rest unchecked).
+- Mark the following files for erasing: `/cert/ca.pem`, `/cert/client.pem`, `/cert/private.key` and `/tmp/pac.bin`.
+- Add a new file with the name of /sys/mcuimg.bin, and select the URL to point to cc3200\bootmgr\build\<BOARD_NAME>\bootloader.bin.
+- Add another file with the name of /sys/factimg.bin, and select the URL to point to cc3200\build\<BOARD_NAME>\mcuimg.bin.
+- Click "Program" to apply all changes.
+- Flash the latest service pack (servicepack_1.0.0.10.0.bin) using the "Service Pack Update" button.
+- Close CCS_Uniflash, remove the SOP2 jumper and reset the board.
+
+## Updating the board to with new software version
+- Make sure the board is running and connected to the same network as the computer.
+
+```bash
+make BTARGET=application BTYPE=release BOARD=LAUNCHXL WIPY_IP=192.168.1.1 WIPY_USER=micro WIPY_PWD=python deploy
+```
+
+If `WIPY_IP`, `WIPY_USER` or `WIPY_PWD` are omitted the default values (the ones shown above) will be used.
+
+## Playing with MicroPython and the CC3200:
+
+Once the software is running, you have two options to access the MicroPython REPL:
+
+- Through telnet. 
+  * Connect to the network created by the board (as boots up in AP mode), **ssid = "wipy-wlan", key = "www.wipy.io"**.
+    * You can also reinitialize the WLAN in station mode and connect to another AP, or in AP mode but with a
+      different ssid and/or key.
+  * Use your favourite telnet client with the following settings: **host = 192.168.1.1, port = 23.**
+  * Log in with **user = "micro" and password = "python"**
+
+The board has a small file system of 192K (WiPy) or 64K (Launchpad) located in the serial flash connected to the CC3200. 
+SD cards are also supported, you can connect any SD card and configure the pinout using the SD class API.
+
+## Uploading scripts:
+
+To upload your MicroPython scripts to the FTP server, open your FTP client of choice and connect to:
+**ftp://192.168.1.1, user = "micro", password = "python"**
+
+I have tested the FTP server with **FileZilla, FireFTP, FireFox, IE and Chrome,** other clients should work as well, but I am 
+not 100% sure of it.
+
+## Upgrading the firmware Over The Air:
+
+OTA software updates can be performed through the FTP server. After building a new **mcuimg.bin** in release mode, upload it to:
+`/flash/sys/mcuimg.bin` it will take around 6s (The TI simplelink file system is quite slow because every file is mirrored for
+safety). You won't see the file being stored inside `/flash/sys/` because it's actually saved bypassing FatFS, but rest assured that
+the file was successfully transferred, and it has been signed with a MD5 checksum to verify its integrity. 
+Now, reset the MCU by pressing the switch on the board, or by typing:
+
+```python
+import machine
+machine.reset()
+```
+
+### Note regarding FileZilla:
+
+Do not use the quick connect button, instead, open the site manager and create a new configuration. In the "General" tab make 
+sure that encryption is set to: "Only use plain FTP (insecure)". In the Transfer Settings tab limit the max number of connections 
+to one, otherwise FileZilla will try to open a second command connection when retrieving and saving files, and for simplicity and 
+to reduce code size, only one command and one data connections are possible.
+

cc3200/application.lds

@@ -0,0 +1,116 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+__stack_size__    = 2K;       /* interrupts are handled within this stack */
+__min_heap_size__ = 8K;
+
+MEMORY
+{
+    SRAMB (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+    SRAM  (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000
+}
+
+ENTRY(ResetISR)
+
+SECTIONS
+{  
+    /* place the FreeRTOS heap (the micropython stack will live here) */
+    .rtos_heap (NOLOAD) :
+    {
+        . = ALIGN(8);
+        *(.rtos_heap*)
+        . = ALIGN(8);
+    } > SRAMB
+
+    .text :
+    {
+        _text = .;
+        KEEP(*(.intvecs))
+        *(.text*)
+        *(.rodata*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        . = ALIGN(8);
+    } > SRAM
+
+    .ARM :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+        _etext = .;
+    } > SRAM
+
+    .data :
+    {
+        . = ALIGN(8);
+        _data = .;
+        *(.data*)
+        . = ALIGN(8);
+        _edata = .;
+    } > SRAM
+
+    .bss :
+    {
+        . = ALIGN(8);
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _ebss = .;
+    } > SRAM
+
+    /* place here functions that are only called during boot up, */
+    /* that way, we can re-use this area for the micropython heap */
+    .boot :
+    {
+        . = ALIGN(8);
+        _boot = .;
+        *(.boot*)
+        . = ALIGN(8);
+        _eboot = .;
+    } > SRAM
+     
+    /* allocate the micropython heap */
+    .heap :
+    {
+        . = ALIGN(8);
+        _heap = .;
+        . = . + __min_heap_size__;
+        . = . + (ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ - ABSOLUTE(.));
+        . = ALIGN(8);
+        _eheap = .;
+    } > SRAM
+
+    /* allocate the main stack */
+    .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :
+    {
+        . = ALIGN(8);
+        _stack = .;
+        . = . + __stack_size__;
+        . = ALIGN(8);
+        _estack = .;
+    } > SRAM
+}

cc3200/application.mk

@@ -0,0 +1,251 @@
+APP_INC =  -I.
+APP_INC += -I..
+APP_INC += -Ifatfs/src
+APP_INC += -Ifatfs/src/drivers
+APP_INC += -IFreeRTOS
+APP_INC += -IFreeRTOS/Source/include
+APP_INC += -IFreeRTOS/Source/portable/GCC/ARM_CM3
+APP_INC += -Iftp
+APP_INC += -Ihal
+APP_INC += -Ihal/inc
+APP_INC += -Imisc
+APP_INC += -Imods
+APP_INC += -I../drivers/cc3100/inc
+APP_INC += -Isimplelink
+APP_INC += -Isimplelink/oslib
+APP_INC += -Itelnet
+APP_INC += -Iutil
+APP_INC += -Ibootmgr
+APP_INC += -I$(BUILD)
+APP_INC += -I$(BUILD)/genhdr
+APP_INC += -I../lib/fatfs
+APP_INC += -I../lib/mp-readline
+APP_INC += -I../lib/netutils
+APP_INC += -I../lib/timeutils
+APP_INC += -I../stmhal
+
+APP_CPPDEFINES = -Dgcc -DTARGET_IS_CC3200 -DSL_FULL -DUSE_FREERTOS
+
+APP_FATFS_SRC_C = $(addprefix fatfs/src/,\
+	drivers/sflash_diskio.c \
+	drivers/sd_diskio.c \
+	option/syscall.c \
+	diskio.c \
+	ffconf.c \
+	)
+
+APP_RTOS_SRC_C = $(addprefix FreeRTOS/Source/,\
+	croutine.c \
+	event_groups.c \
+	list.c \
+	queue.c \
+	tasks.c \
+	timers.c \
+	portable/GCC/ARM_CM3/port.c \
+	portable/MemMang/heap_4.c \
+	)
+
+APP_FTP_SRC_C = $(addprefix ftp/,\
+	ftp.c \
+	updater.c \
+	)
+
+APP_HAL_SRC_C = $(addprefix hal/,\
+	adc.c \
+	aes.c \
+	cc3200_hal.c \
+	cpu.c \
+	crc.c \
+	des.c \
+	gpio.c \
+	i2c.c \
+	i2s.c \
+	interrupt.c \
+	pin.c \
+	prcm.c \
+	sdhost.c \
+	shamd5.c \
+	spi.c \
+	startup_gcc.c \
+	systick.c \
+	timer.c \
+	uart.c \
+	utils.c \
+	wdt.c \
+	)
+
+APP_MISC_SRC_C = $(addprefix misc/,\
+	antenna.c \
+	FreeRTOSHooks.c \
+	help.c \
+	mpirq.c \
+	mperror.c \
+	mpexception.c \
+	mpsystick.c \
+	)
+
+APP_MODS_SRC_C = $(addprefix mods/,\
+	modmachine.c \
+	modnetwork.c \
+	modubinascii.c \
+	moduos.c \
+	modusocket.c \
+	modussl.c \
+	modutime.c \
+	modwipy.c \
+	modwlan.c \
+	pybadc.c \
+	pybpin.c \
+	pybi2c.c \
+	pybrtc.c \
+	pybsd.c \
+	pybsleep.c \
+	pybspi.c \
+	pybtimer.c \
+	pybuart.c \
+	pybwdt.c \
+	)
+
+APP_CC3100_SRC_C = $(addprefix drivers/cc3100/src/,\
+	device.c \
+	driver.c \
+	flowcont.c \
+	fs.c \
+	netapp.c \
+	netcfg.c \
+	socket.c \
+	wlan.c \
+	)
+
+APP_SL_SRC_C = $(addprefix simplelink/,\
+	oslib/osi_freertos.c \
+	cc_pal.c \
+	) 
+
+APP_TELNET_SRC_C = $(addprefix telnet/,\
+	telnet.c \
+	)
+	
+APP_UTIL_SRC_C = $(addprefix util/,\
+	cryptohash.c \
+	fifo.c \
+	gccollect.c \
+	random.c \
+	socketfifo.c \
+	)
+	
+APP_UTIL_SRC_S = $(addprefix util/,\
+	gchelper.s \
+	sleeprestore.s \
+	)
+	
+APP_MAIN_SRC_C = \
+	main.c \
+	mptask.c \
+	mpthreadport.c \
+	serverstask.c
+	
+APP_LIB_SRC_C = $(addprefix lib/,\
+	fatfs/ff.c \
+	fatfs/option/ccsbcs.c \
+	libc/string0.c \
+	mp-readline/readline.c \
+	netutils/netutils.c \
+	timeutils/timeutils.c \
+	utils/pyexec.c \
+	utils/pyhelp.c \
+	)
+	
+APP_STM_SRC_C = $(addprefix stmhal/,\
+	bufhelper.c \
+	builtin_open.c \
+	import.c \
+	input.c \
+	irq.c \
+	lexerfatfs.c \
+	moduselect.c \
+	pybstdio.c \
+	)
+
+OBJ = $(PY_O) $(addprefix $(BUILD)/, $(APP_FATFS_SRC_C:.c=.o) $(APP_RTOS_SRC_C:.c=.o) $(APP_FTP_SRC_C:.c=.o) $(APP_HAL_SRC_C:.c=.o) $(APP_MISC_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(APP_MODS_SRC_C:.c=.o) $(APP_CC3100_SRC_C:.c=.o) $(APP_SL_SRC_C:.c=.o) $(APP_TELNET_SRC_C:.c=.o) $(APP_UTIL_SRC_C:.c=.o) $(APP_UTIL_SRC_S:.s=.o))
+OBJ += $(addprefix $(BUILD)/, $(APP_MAIN_SRC_C:.c=.o) $(APP_LIB_SRC_C:.c=.o) $(APP_STM_SRC_C:.c=.o))
+OBJ += $(BUILD)/pins.o
+
+# List of sources for qstr extraction
+SRC_QSTR += $(APP_MODS_SRC_C) $(APP_MISC_SRC_C) $(APP_STM_SRC_C)
+# Append any auto-generated sources that are needed by sources listed in
+# SRC_QSTR
+SRC_QSTR_AUTO_DEPS +=
+
+# Add the linker script
+LINKER_SCRIPT = application.lds
+LDFLAGS += -T $(LINKER_SCRIPT)
+
+# Add the application specific CFLAGS
+CFLAGS += $(APP_CPPDEFINES) $(APP_INC)
+
+# Disable strict aliasing for the simplelink driver
+$(BUILD)/drivers/cc3100/src/driver.o: CFLAGS += -fno-strict-aliasing
+
+# Check if we would like to debug the port code
+ifeq ($(BTYPE), release)
+CFLAGS += -DNDEBUG
+else
+ifeq ($(BTYPE), debug)
+CFLAGS += -DNDEBUG
+else
+$(error Invalid BTYPE specified)
+endif
+endif
+
+SHELL = bash
+APP_SIGN = appsign.sh
+UPDATE_WIPY ?= tools/update-wipy.py
+WIPY_IP ?= '192.168.1.1'
+WIPY_USER ?= 'micro'
+WIPY_PWD ?= 'python'
+
+all: $(BUILD)/mcuimg.bin
+
+.PHONY: deploy
+
+deploy: $(BUILD)/mcuimg.bin
+	$(ECHO) "Writing $< to the board"
+	$(Q)$(PYTHON) $(UPDATE_WIPY) --verify --ip $(WIPY_IP) --user $(WIPY_USER) --password $(WIPY_PWD) --file $<
+
+$(BUILD)/application.axf: $(OBJ) $(LINKER_SCRIPT)
+	$(ECHO) "LINK $@"
+	$(Q)$(CC) -o $@ $(LDFLAGS) $(OBJ) $(LIBS)
+	$(Q)$(SIZE) $@
+
+$(BUILD)/application.bin: $(BUILD)/application.axf
+	$(ECHO) "Create $@"
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+$(BUILD)/mcuimg.bin: $(BUILD)/application.bin
+	$(ECHO) "Create $@"
+	$(Q)$(SHELL) $(APP_SIGN) $(BUILD)
+
+MAKE_PINS = boards/make-pins.py
+BOARD_PINS = boards/$(BOARD)/pins.csv
+AF_FILE = boards/cc3200_af.csv
+PREFIX_FILE = boards/cc3200_prefix.c
+GEN_PINS_SRC = $(BUILD)/pins.c
+GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
+GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
+
+# Making OBJ use an order-only dependency on the generated pins.h file
+# has the side effect of making the pins.h file before we actually compile
+# any of the objects. The normal dependency generation will deal with the
+# case when pins.h is modified. But when it doesn't exist, we don't know
+# which source files might need it.
+$(OBJ): | $(GEN_PINS_HDR)
+
+# Call make-pins.py to generate both pins_gen.c and pins.h
+$(GEN_PINS_SRC) $(GEN_PINS_HDR) $(GEN_PINS_QSTR): $(BOARD_PINS) $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD)
+	$(ECHO) "Create $@"
+	$(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) > $(GEN_PINS_SRC)
+
+$(BUILD)/pins.o: $(BUILD)/pins.c
+	$(call compile_c)

cc3200/appsign.sh

@@ -0,0 +1,29 @@
+#!/bin/bash
+
+if [ "$#" -ne 1 ]; then
+    echo "Usage: appsign.sh *build dir*"
+    exit 1
+fi
+
+# Build location
+BUILD=$1
+
+# Generate the MD5 hash
+# md5 on Darwin, md5sum on Unix
+if [ `uname -s` = "Darwin" ]; then
+echo -n `md5 -q $BUILD/application.bin` > __md5hash.bin
+else
+echo -n `md5sum --binary $BUILD/application.bin | awk '{ print $1 }'` > __md5hash.bin
+fi
+
+# Concatenate it with the application binary
+cat $BUILD/application.bin __md5hash.bin > $BUILD/mcuimg.bin
+RET=$?
+
+# Remove the tmp files
+rm -f __md5hash.bin
+
+# Remove the unsigned binary
+rm -f $BUILD/application.bin
+
+exit $RET

cc3200/boards/LAUNCHXL/mpconfigboard.h

@@ -0,0 +1,49 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define LAUNCHXL
+
+#define MICROPY_HW_BOARD_NAME                       "LaunchPad"
+#define MICROPY_HW_MCU_NAME                         "CC3200"
+
+#define MICROPY_HW_ANTENNA_DIVERSITY                (0)
+
+#define MICROPY_STDIO_UART                          0
+#define MICROPY_STDIO_UART_BAUD                     115200
+
+#define MICROPY_SYS_LED_PRCM                        PRCM_GPIOA1
+#define MICROPY_SAFE_BOOT_PRCM                      PRCM_GPIOA2
+#define MICROPY_SYS_LED_PORT                        GPIOA1_BASE
+#define MICROPY_SAFE_BOOT_PORT                      GPIOA2_BASE
+#define MICROPY_SYS_LED_GPIO                        pin_GP9
+#define MICROPY_SYS_LED_PIN_NUM                     PIN_64      // GP9
+#define MICROPY_SAFE_BOOT_PIN_NUM                   PIN_15      // GP22
+#define MICROPY_SYS_LED_PORT_PIN                    GPIO_PIN_1
+#define MICROPY_SAFE_BOOT_PORT_PIN                  GPIO_PIN_6
+
+#define MICROPY_PORT_SFLASH_BLOCK_COUNT             32
+

cc3200/boards/LAUNCHXL/pins.csv

@@ -0,0 +1,25 @@
+P12,58
+P13,4
+P14,3
+P15,61
+P16,59
+P17,5
+P18,62
+P19,1
+P110,2
+P33,57
+P34,60
+P37,63
+P38,53
+P39,64
+P310,50
+P49,16
+P410,17
+P22,18
+P23,8
+P24,45
+P26,7
+P27,6
+P28,21
+P29,55
+P210,15

cc3200/boards/WIPY/mpconfigboard.h

@@ -0,0 +1,45 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define WIPY
+
+#define MICROPY_HW_BOARD_NAME                       "WiPy"
+#define MICROPY_HW_MCU_NAME                         "CC3200"
+
+#define MICROPY_HW_ANTENNA_DIVERSITY                (1)
+
+#define MICROPY_SYS_LED_PRCM                        PRCM_GPIOA3
+#define MICROPY_SAFE_BOOT_PRCM                      PRCM_GPIOA3
+#define MICROPY_SYS_LED_PORT                        GPIOA3_BASE
+#define MICROPY_SAFE_BOOT_PORT                      GPIOA3_BASE
+#define MICROPY_SYS_LED_GPIO                        pin_GP25
+#define MICROPY_SYS_LED_PIN_NUM                     PIN_21      // GP25   (SOP2)
+#define MICROPY_SAFE_BOOT_PIN_NUM                   PIN_18      // GP28
+#define MICROPY_SYS_LED_PORT_PIN                    GPIO_PIN_1
+#define MICROPY_SAFE_BOOT_PORT_PIN                  GPIO_PIN_4
+
+#define MICROPY_PORT_SFLASH_BLOCK_COUNT             96

cc3200/boards/WIPY/pins.csv

@@ -0,0 +1,25 @@
+L2,GP2
+L3,GP1
+L4,GP23
+L5,GP24
+L6,GP11
+L7,GP12
+L8,GP13
+L9,GP14
+L10,GP15
+L11,GP16
+L12,GP17
+L13,GP22
+L14,GP28
+R4,GP10
+R5,GP9
+R6,GP8
+R7,GP7
+R8,GP6
+R9,GP30
+R10,GP31
+R11,GP3
+R12,GP0
+R13,GP4
+R14,GP5
+HBL,GP25

cc3200/boards/cc3200_af.csv

@@ -0,0 +1,66 @@
+Pin,Name,Default,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,ADC
+1,GP10,GP10,GP10,I2C0_SCL,,TIM3_PWM,,,SD0_CLK,UART1_TX,,,,,TIM0_CC,,,,
+2,GP11,GP11,GP11,I2C0_SDA,,TIM3_PWM,pXCLK(XVCLK),,SD0_CMD,UART1_RX,,,,,TIM1_CC,I2S0_FS,,,
+3,GP12,GP12,GP12,,,I2S0_CLK,pVS(VSYNC),I2C0_SCL,,UART0_TX,,,,,TIM1_CC,,,,
+4,GP13,GP13,GP13,,,,pHS(HSYNC),I2C0_SDA,,UART0_RX,,,,,TIM2_CC,,,,
+5,GP14,GP14,GP14,,,,pDATA8(CAM_D4),I2C0_SCL,,SPI0_CLK,,,,,TIM2_CC,,,,
+6,GP15,GP15,GP15,,,,pDATA9(CAM_D5),I2C0_SDA,,SPI0_MISO,SD0_DAT0,,,,,TIM3_CC,,,
+7,GP16,GP16,GP16,,,,pDATA10(CAM_D6),UART1_TX,,SPI0_MOSI,SD0_CLK,,,,,TIM3_CC,,,
+8,GP17,GP17,GP17,,,,pDATA11(CAM_D7),UART1_RX,,SPI0_CS0,SD0_CMD,,,,,,,,
+9,VDD_DIG1,VDD_DIG1,VDD_DIG1,,,,,,,,,,,,,,,,
+10,VIN_IO1,VIN_IO1,VIN_IO1,,,,,,,,,,,,,,,,
+11,FLASH_SPI_CLK,FLASH_SPI_CLK,FLASH_SPI_CLK,,,,,,,,,,,,,,,,
+12,FLASH_SPI_DOUT,FLASH_SPI_DOUT,FLASH_SPI_DOUT,,,,,,,,,,,,,,,,
+13,FLASH_SPI_DIN,FLASH_SPI_DIN,FLASH_SPI_DIN,,,,,,,,,,,,,,,,
+14,FLASH_SPI_CS,FLASH_SPI_CS,FLASH_SPI_CS,,,,,,,,,,,,,,,,
+15,GP22,GP22,GP22,,,,,TIM2_CC,,I2S0_FS,,,,,,,,,
+16,GP23,TDI,GP23,TDI,UART1_TX,,,,,,,I2C0_SCL,,,,,,,
+17,GP24,TDO,GP24,TDO,UART1_RX,,TIM3_CC,TIM0_PWM,I2S0_FS,,,I2C0_SDA,,,,,,,
+18,GP28,GP28,GP28,,,,,,,,,,,,,,,,
+19,TCK,TCK,,TCK,,,,,,,TIM1_PWM,,,,,,,,
+20,GP29,TMS,GP29,TMS,,,,,,,,,,,,,,,
+21,GP25,SOP2,GP25,,I2S0_FS,,,,,,,TIM1_PWM,,,,,,,
+22,WLAN_XTAL_N,WLAN_XTAL_N,WLAN_XTAL_N,,,,,,,,,,,,,,,,
+23,WLAN_XTAL_P,WLAN_XTAL_P,WLAN_XTAL_P,,,,,,,,,,,,,,,,
+24,VDD_PLL,VDD_PLL,VDD_PLL,,,,,,,,,,,,,,,,
+25,LDO_IN2,LDO_IN2,LDO_IN2,,,,,,,,,,,,,,,,
+26,NC,NC,NC,,,,,,,,,,,,,,,,
+27,NC,NC,NC,,,,,,,,,,,,,,,,
+28,NC,NC,NC,,,,,,,,,,,,,,,,
+29,ANTSEL1,ANTSEL1,ANTSEL1,,,,,,,,,,,,,,,,
+30,ANTSEL2,ANTSEL2,ANTSEL2,,,,,,,,,,,,,,,,
+31,RF_BG,RF_BG,RF_BG,,,,,,,,,,,,,,,,
+32,nRESET,nRESET,nRESET,,,,,,,,,,,,,,,,
+33,VDD_PA_IN,VDD_PA_IN,VDD_PA_IN,,,,,,,,,,,,,,,,
+34,SOP1,SOP1,SOP1,,,,,,,,,,,,,,,,
+35,SOP0,SOP0,SOP0,,,,,,,,,,,,,,,,
+36,LDO_IN1,LDO_IN1,LDO_IN1,,,,,,,,,,,,,,,,
+37,VIN_DCDC_ANA,VIN_DCDC_ANA,VIN_DCDC_ANA,,,,,,,,,,,,,,,,
+38,DCDC_ANA_SW,DCDC_ANA_SW,DCDC_ANA_SW,,,,,,,,,,,,,,,,
+39,VIN_DCDC_PA,VIN_DCDC_ PA,VIN_DCDC_PA,,,,,,,,,,,,,,,,
+40,DCDC_PA_SW_P,DCDC_PA_SW_P,DCDC_PA_SW_P,,,,,,,,,,,,,,,,
+41,DCDC_PA_SW_N,DCDC_PA_SW_N,DCDC_PA_SW_N,,,,,,,,,,,,,,,,
+42,DCDC_PA_OUT,DCDC_PA_O UT,DCDC_PA_O UT,,,,,,,,,,,,,,,,
+43,DCDC_DIG_SW,DCDC_DIG_ SW,DCDC_DIG_ SW,,,,,,,,,,,,,,,,
+44,VIN_DCDC_DIG,VIN_DCDC_ DIG,VIN_DCDC_ DIG,,,,,,,,,,,,,,,,
+45,GP31,DCDC_ANA2_SW_P,GP31,,UART1_RX,,,,I2S0_DAT0,SPI0_CLK,,UART0_RX,,,I2S0_FS,,,,
+46,DCDC_ANA2_SW_N,DCDC_ANA2_SW_N,DCDC_ANA2_SW_N,,,,,,,,,,,,,,,,
+47,VDD_ANA2,VDD_ANA2,VDD_ANA2,,,,,,,,,,,,,,,,
+48,VDD_ANA1,VDD_ANA1,VDD_ANA1,,,,,,,,,,,,,,,,
+49,VDD_RAM,VDD_RAM,VDD_RAM,,,,,,,,,,,,,,,,
+50,GP0,GP0,GP0,,,UART0_RTS,I2S0_DAT0,,I2S0_DAT1,TIM0_CC,,SPI0_CS0,UART1_RTS,,UART0_CTS,,,,
+51,RTC_XTAL_P,RTC_XTAL_P,RTC_XTAL_P,,,,,,,,,,,,,,,,
+52,RTC_XTAL_N,RTC_XTAL_N,GP32,,I2S0_CLK,,I2S0_DAT0,,UART0_RTS,,SPI0_MOSI,,,,,,,,
+53,GP30,GP30,GP30,,I2S0_CLK,I2S0_FS,TIM2_CC,,,SPI0_MISO,,UART0_TX,,,,,,,
+54,VIN_IO2,VIN_IO2,VIN_IO2,,,,,,,,,,,,,,,,
+55,GP1,GP1,GP1,,,UART0_TX,pCLK (PIXCLK),,UART1_TX,TIM0_CC,,,,,,,,,
+56,VDD_DIG2,VDD_DIG2,VDD_DIG2,,,,,,,,,,,,,,,,
+57,GP2,GP2,GP2,,,UART0_RX,,,UART1_RX,TIM1_CC,,,,,,,,,ADC0_CH0
+58,GP3,GP3,GP3,,,,pDATA7(CAM_D3),,UART1_TX,,,,,,,,,,ADC0_CH1
+59,GP4,GP4,GP4,,,,pDATA6(CAM_D2),,UART1_RX,,,,,,,,,,ADC0_CH2
+60,GP5,GP5,GP5,,,,pDATA5(CAM_D1),,I2S0_DAT1,TIM2_CC,,,,,,,,,ADC0_CH3
+61,GP6,GP6,GP6,,,UART1_CTS,pDATA4(CAM_D0),UART0_RTS,UART0_CTS,TIM3_CC,,,,,,,,,
+62,GP7,GP7,GP7,,,UART1_RTS,,,,,,,UART0_RTS,UART0_TX,,I2S0_CLK,,,
+63,GP8,GP8,GP8,,,,,,SD0_IRQ,I2S0_FS,,,,,TIM3_CC,,,,
+64,GP9,GP9,GP9,,,TIM2_PWM,,,SD0_DAT0,I2S0_DAT0,,,,,TIM0_CC,,,,
+65,GND_TAB,GND_TAB,GND_TAB,,,,,,,,,,,,,,,,

cc3200/boards/cc3200_prefix.c

@@ -0,0 +1,69 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// cc3200_prefix.c becomes the initial portion of the generated pins file.
+
+#include <stdio.h>
+#include <stdint.h>
+
+#include "py/mpconfig.h"
+#include "py/obj.h"
+#include "inc/hw_types.h"
+#include "inc/hw_memmap.h"
+#include "pin.h"
+#include "gpio.h"
+#include "pybpin.h"
+
+
+#define AF(af_name, af_idx, af_fn, af_unit, af_type) \
+{ \
+    .name = MP_QSTR_ ## af_name, \
+    .idx = (af_idx), \
+    .fn = PIN_FN_ ## af_fn, \
+    .unit = (af_unit), \
+    .type = PIN_TYPE_ ## af_fn ## _ ## af_type, \
+}
+
+
+#define PIN(p_pin_name, p_port, p_bit, p_pin_num, p_af_list, p_num_afs) \
+{ \
+    { &pin_type }, \
+    .name           = MP_QSTR_ ## p_pin_name, \
+    .port           = PORT_A ## p_port, \
+    .af_list        = (p_af_list), \
+    .pull           = PIN_TYPE_STD, \
+    .bit            = (p_bit), \
+    .pin_num        = (p_pin_num), \
+    .af             = PIN_MODE_0, \
+    .strength       = PIN_STRENGTH_4MA, \
+    .mode           = GPIO_DIR_MODE_IN, \
+    .num_afs        = (p_num_afs), \
+    .value          = 0, \
+    .used           = false, \
+    .irq_trigger    = 0, \
+    .irq_flags      = 0, \
+}

cc3200/boards/make-pins.py

@@ -0,0 +1,233 @@
+#!/usr/bin/env python
+"""Generates the pins file for the CC3200."""
+
+from __future__ import print_function
+
+import argparse
+import sys
+import csv
+
+
+SUPPORTED_AFS = { 'UART': ('TX', 'RX', 'RTS', 'CTS'),
+                  'SPI': ('CLK', 'MOSI', 'MISO', 'CS0'),
+                  #'I2S': ('CLK', 'FS', 'DAT0', 'DAT1'),
+                  'I2C': ('SDA', 'SCL'),
+                  'TIM': ('PWM'),
+                  'SD': ('CLK', 'CMD', 'DAT0'),
+                  'ADC': ('CH0', 'CH1', 'CH2', 'CH3')
+                }
+
+def parse_port_pin(name_str):
+    """Parses a string and returns a (port, gpio_bit) tuple."""
+    if len(name_str) < 3:
+        raise ValueError("Expecting pin name to be at least 3 characters")
+    if name_str[:2] != 'GP':
+        raise ValueError("Expecting pin name to start with GP")
+    if not name_str[2:].isdigit():
+        raise ValueError("Expecting numeric GPIO number")
+    port = int(int(name_str[2:]) / 8)
+    gpio_bit = 1 << int(int(name_str[2:]) % 8)
+    return (port, gpio_bit)
+
+
+class AF:
+    """Holds the description of an alternate function"""
+    def __init__(self, name, idx, fn, unit, type):
+        self.name = name
+        self.idx = idx
+        if self.idx > 15:
+            self.idx = -1
+        self.fn = fn
+        self.unit = unit
+        self.type = type
+
+    def print(self):
+        print ('    AF({:16s}, {:4d}, {:8s}, {:4d}, {:8s}),    // {}'.format(self.name, self.idx, self.fn, self.unit, self.type, self.name))
+
+
+class Pin:
+    """Holds the information associated with a pin."""
+    def __init__(self, name, port, gpio_bit, pin_num):
+        self.name = name
+        self.port = port
+        self.gpio_bit = gpio_bit
+        self.pin_num = pin_num
+        self.board_pin = False
+        self.afs = []
+
+    def add_af(self, af):
+        self.afs.append(af)
+
+    def print(self):
+        print('// {}'.format(self.name))
+        if len(self.afs):
+            print('const pin_af_t pin_{}_af[] = {{'.format(self.name))
+            for af in self.afs:
+                af.print()
+            print('};')
+            print('pin_obj_t pin_{:4s} = PIN({:6s}, {:1d}, {:3d}, {:2d}, pin_{}_af, {});\n'.format(
+                   self.name, self.name, self.port, self.gpio_bit, self.pin_num, self.name, len(self.afs)))
+        else:
+            print('pin_obj_t pin_{:4s} = PIN({:6s}, {:1d}, {:3d}, {:2d}, NULL, 0);\n'.format(
+                   self.name, self.name, self.port, self.gpio_bit, self.pin_num))
+
+    def print_header(self, hdr_file):
+        hdr_file.write('extern pin_obj_t pin_{:s};\n'.format(self.name))
+
+
+class Pins:
+    def __init__(self):
+        self.board_pins = []   # list of pin objects
+
+    def find_pin(self, port, gpio_bit):
+        for pin in self.board_pins:
+            if pin.port == port and pin.gpio_bit == gpio_bit:
+                return pin
+
+    def find_pin_by_num(self, pin_num):
+        for pin in self.board_pins:
+            if pin.pin_num == pin_num:
+                return pin
+
+    def find_pin_by_name(self, name):
+        for pin in self.board_pins:
+            if pin.name == name:
+                return pin
+
+    def parse_af_file(self, filename, pin_col, pinname_col, af_start_col):
+        with open(filename, 'r') as csvfile:
+            rows = csv.reader(csvfile)
+            for row in rows:
+                try:
+                    (port_num, gpio_bit) = parse_port_pin(row[pinname_col])
+                except:
+                    continue
+                if not row[pin_col].isdigit():
+                    raise ValueError("Invalid pin number {:s} in row {:s}".format(row[pin_col]), row)
+                # Pin numbers must start from 0 when used with the TI API
+                pin_num = int(row[pin_col]) - 1;        
+                pin = Pin(row[pinname_col], port_num, gpio_bit, pin_num)
+                self.board_pins.append(pin)
+                af_idx = 0
+                for af in row[af_start_col:]:
+                    af_splitted = af.split('_')
+                    fn_name = af_splitted[0].rstrip('0123456789')
+                    if  fn_name in SUPPORTED_AFS:
+                        type_name = af_splitted[1]
+                        if type_name in SUPPORTED_AFS[fn_name]:
+                            unit_idx = af_splitted[0][-1]
+                            pin.add_af(AF(af, af_idx, fn_name, int(unit_idx), type_name))
+                    af_idx += 1
+
+    def parse_board_file(self, filename, cpu_pin_col):
+        with open(filename, 'r') as csvfile:
+            rows = csv.reader(csvfile)
+            for row in rows:
+                # Pin numbers must start from 0 when used with the TI API
+                if row[cpu_pin_col].isdigit():
+                    pin = self.find_pin_by_num(int(row[cpu_pin_col]) - 1)
+                else:
+                    pin = self.find_pin_by_name(row[cpu_pin_col])
+                if pin:
+                    pin.board_pin = True
+
+    def print_named(self, label, pins):
+        print('')
+        print('STATIC const mp_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{'.format(label))
+        for pin in pins:
+            if pin.board_pin:
+                print('    {{ MP_OBJ_NEW_QSTR(MP_QSTR_{:6s}), (mp_obj_t)&pin_{:6s} }},'.format(pin.name, pin.name))
+        print('};')
+        print('MP_DEFINE_CONST_DICT(pin_{:s}_pins_locals_dict, pin_{:s}_pins_locals_dict_table);'.format(label, label));
+
+    def print(self):
+        for pin in self.board_pins:
+            if pin.board_pin:
+                pin.print()
+        self.print_named('board', self.board_pins)
+        print('')
+
+    def print_header(self, hdr_filename):
+        with open(hdr_filename, 'wt') as hdr_file:
+            for pin in self.board_pins:
+                if pin.board_pin:
+                    pin.print_header(hdr_file)
+
+    def print_qstr(self, qstr_filename):
+        with open(qstr_filename, 'wt') as qstr_file:
+            pin_qstr_set = set([])
+            af_qstr_set = set([])
+            for pin in self.board_pins:
+                if pin.board_pin:
+                    pin_qstr_set |= set([pin.name])
+                    for af in pin.afs:
+                        af_qstr_set |= set([af.name])
+            print('// Board pins', file=qstr_file)
+            for qstr in sorted(pin_qstr_set):
+                print('Q({})'.format(qstr), file=qstr_file)
+            print('\n// Pin AFs', file=qstr_file)
+            for qstr in sorted(af_qstr_set):
+                print('Q({})'.format(qstr), file=qstr_file)
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        prog="make-pins.py",
+        usage="%(prog)s [options] [command]",
+        description="Generate board specific pin file"
+    )
+    parser.add_argument(
+        "-a", "--af",
+        dest="af_filename",
+        help="Specifies the alternate function file for the chip",
+        default="cc3200_af.csv"
+    )
+    parser.add_argument(
+        "-b", "--board",
+        dest="board_filename",
+        help="Specifies the board file",
+    )
+    parser.add_argument(
+        "-p", "--prefix",
+        dest="prefix_filename",
+        help="Specifies beginning portion of generated pins file",
+        default="cc3200_prefix.c"
+    )
+    parser.add_argument(
+        "-q", "--qstr",
+        dest="qstr_filename",
+        help="Specifies name of generated qstr header file",
+        default="build/pins_qstr.h"
+    )
+    parser.add_argument(
+        "-r", "--hdr",
+        dest="hdr_filename",
+        help="Specifies name of generated pin header file",
+        default="build/pins.h"
+    )
+    args = parser.parse_args(sys.argv[1:])
+
+    pins = Pins()
+
+    print('// This file was automatically generated by make-pins.py')
+    print('//')
+    if args.af_filename:
+        print('// --af {:s}'.format(args.af_filename))
+        pins.parse_af_file(args.af_filename, 0, 1, 3)
+
+    if args.board_filename:
+        print('// --board {:s}'.format(args.board_filename))
+        pins.parse_board_file(args.board_filename, 1)
+
+    if args.prefix_filename:
+        print('// --prefix {:s}'.format(args.prefix_filename))
+        print('')
+        with open(args.prefix_filename, 'r') as prefix_file:
+            print(prefix_file.read())
+    pins.print()
+    pins.print_qstr(args.qstr_filename)
+    pins.print_header(args.hdr_filename)
+
+
+if __name__ == "__main__":
+    main()

cc3200/bootmgr/bootgen.sh

@@ -0,0 +1,50 @@
+#!/bin/bash
+
+if [ "$#" -ne 1 ]; then
+    echo "Usage: bootgen.sh *build dir*"
+    exit 1
+fi
+
+BUILD=$1
+
+# Re-locator Path
+RELOCATOR=bootmgr/relocator
+
+# Build location
+BOOTMGR=${BUILD}
+
+# Check for re-locator binary
+if [ ! -f $RELOCATOR/relocator.bin ]; then
+
+	echo "Error : Relocator Not found!"
+	exit 1
+else
+	echo "Relocator found..."
+fi
+
+# Check for boot manager binary
+if [ ! -f $BOOTMGR/bootmgr.bin ]; then
+
+	echo "Error : Boot Manager Not found!"
+	exit 1
+else
+	echo "Boot Manager found..."
+fi
+
+# echo
+echo "Generating bootloader..."
+
+# Generate an all 0 bin file
+dd if=/dev/zero of=__tmp.bin ibs=1 count=256 conv=notrunc >/dev/null 2>&1
+
+# Generate a 0 padded version of the relocator 
+dd if=$RELOCATOR/relocator.bin of=__tmp.bin ibs=1 conv=notrunc >/dev/null 2>&1
+
+# Concatenate the re-locator and the boot-manager
+cat __tmp.bin $BOOTMGR/bootmgr.bin > $BOOTMGR/bootloader.bin
+
+# Remove the tmp files
+rm -f __tmp.bin
+
+# Remove bootmgr.bin
+rm -f $BOOTMGR/bootmgr.bin

cc3200/bootmgr/bootloader.mk

@@ -0,0 +1,132 @@
+BUILD = bootmgr/build/$(BOARD)/$(BTYPE)
+
+BOOT_INC  = -Ibootmgr
+BOOT_INC += -Ibootmgr/sl
+BOOT_INC += -Ihal
+BOOT_INC += -Ihal/inc
+BOOT_INC += -I../drivers/cc3100/inc
+BOOT_INC += -Imisc
+BOOT_INC += -Imods
+BOOT_INC += -Isimplelink
+BOOT_INC += -Isimplelink/oslib
+BOOT_INC += -Iutil
+BOOT_INC += -I..
+BOOT_INC += -I.
+BOOT_INC += -I$(BUILD)
+
+BOOT_CPPDEFINES = -Dgcc -DBOOTLOADER -DTARGET_IS_CC3200 -DSL_TINY
+
+BOOT_HAL_SRC_C = $(addprefix hal/,\
+	cpu.c \
+	interrupt.c \
+	gpio.c \
+	pin.c \
+	prcm.c \
+	shamd5.c \
+	spi.c \
+	startup_gcc.c \
+	systick.c \
+	utils.c \
+	)
+
+BOOT_CC3100_SRC_C = $(addprefix drivers/cc3100/,\
+	src/device.c \
+	src/driver.c \
+	src/flowcont.c \
+	src/fs.c \
+	src/netapp.c \
+	src/netcfg.c \
+	src/nonos.c \
+	src/socket.c \
+	src/spawn.c \
+	src/wlan.c \
+	)
+
+BOOT_MISC_SRC_C = $(addprefix misc/,\
+	antenna.c \
+	mperror.c \
+	)
+
+BOOT_SL_SRC_C = $(addprefix simplelink/,\
+	cc_pal.c \
+	)
+
+BOOT_UTIL_SRC_C = $(addprefix util/,\
+	cryptohash.c \
+	) 
+
+BOOT_MAIN_SRC_C = \
+	bootmgr/main.c
+
+BOOT_MAIN_SRC_S = \
+	bootmgr/runapp.s
+
+BOOT_PY_SRC_C = $(addprefix py/,\
+	mpprint.c \
+	)
+
+BOOT_LIB_SRC_C = $(addprefix lib/,\
+	libc/string0.c \
+	utils/printf.c \
+	)
+
+OBJ  = $(addprefix $(BUILD)/, $(BOOT_HAL_SRC_C:.c=.o) $(BOOT_SL_SRC_C:.c=.o) $(BOOT_CC3100_SRC_C:.c=.o) $(BOOT_UTIL_SRC_C:.c=.o) $(BOOT_MISC_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(BOOT_MAIN_SRC_C:.c=.o) $(BOOT_MAIN_SRC_S:.s=.o) $(BOOT_PY_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(BOOT_LIB_SRC_C:.c=.o))
+
+# Add the linker script
+LINKER_SCRIPT = bootmgr/bootmgr.lds
+LDFLAGS += -T $(LINKER_SCRIPT)
+
+# Add the bootloader specific CFLAGS
+CFLAGS += $(BOOT_CPPDEFINES) $(BOOT_INC)
+
+# Disable strict aliasing for the simplelink driver
+$(BUILD)/drivers/cc3100/src/driver.o: CFLAGS += -fno-strict-aliasing
+
+# Check if we would like to debug the port code
+ifeq ($(BTYPE), release)
+# Optimize everything and define the NDEBUG flag
+CFLAGS += -Os -DNDEBUG
+else
+ifeq ($(BTYPE), debug)
+# Define the DEBUG flag
+CFLAGS += -DDEBUG=DEBUG
+# Optimize the stable sources only
+$(BUILD)/hal/%.o: CFLAGS += -Os
+$(BUILD)/misc/%.o: CFLAGS += -Os
+$(BUILD)/simplelink/%.o: CFLAGS += -Os
+$(BUILD)/drivers/cc3100/%.o: CFLAGS += -Os
+$(BUILD)/py/%.o: CFLAGS += -Os
+$(BUILD)/stmhal/%.o: CFLAGS += -Os
+else
+$(error Invalid BTYPE specified)
+endif
+endif
+
+SHELL = bash
+BOOT_GEN = bootmgr/bootgen.sh
+HEADER_BUILD = $(BUILD)/genhdr
+
+all: $(BUILD)/bootloader.bin
+
+$(BUILD)/bootmgr.axf: $(OBJ) $(LINKER_SCRIPT)
+	$(ECHO) "LINK $@"
+	$(Q)$(CC) -o $@ $(LDFLAGS) $(OBJ) $(LIBS)
+	$(Q)$(SIZE) $@
+	
+$(BUILD)/bootmgr.bin: $(BUILD)/bootmgr.axf
+	$(ECHO) "Create $@"
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+$(BUILD)/bootloader.bin: $(BUILD)/bootmgr.bin
+	$(ECHO) "Create $@"
+	$(Q)$(SHELL) $(BOOT_GEN) $(BUILD)
+
+# Create an empty "qstrdefs.generated.h" needed by py/mkrules.mk
+$(HEADER_BUILD)/qstrdefs.generated.h: | $(HEADER_BUILD)
+	touch $@
+
+# Create an empty "mpversion.h" needed by py/mkrules.mk
+$(HEADER_BUILD)/mpversion.h: | $(HEADER_BUILD)
+	touch $@

cc3200/bootmgr/bootmgr.h

@@ -0,0 +1,69 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __BOOTMGR_H__
+#define __BOOTMGR_H__
+
+//****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+// User image tokens
+//*****************************************************************************
+#define FACTORY_IMG_TOKEN       0x5555AAAA
+#define UPDATE_IMG_TOKEN        0xAA5555AA
+#define USER_BOOT_INFO_TOKEN    0xA5A55A5A
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define APP_IMG_SRAM_OFFSET     0x20004000
+#define DEVICE_IS_CC3101RS      0x18
+#define DEVICE_IS_CC3101S       0x1B
+
+//*****************************************************************************
+// Function prototype
+//*****************************************************************************
+extern void Run(unsigned long);
+
+//****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__BOOTMGR_H__

cc3200/bootmgr/bootmgr.lds

@@ -0,0 +1,82 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+__stack_size__  = 1024;
+
+MEMORY
+{
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+    .text :
+    {
+        _text = .;
+        KEEP(*(.intvecs))
+        *(.boot*)
+        *(.text*)
+        *(.rodata*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        . = ALIGN(8);
+    } > SRAM
+
+    .ARM :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+        _etext = .;
+    } > SRAM
+
+    .data :
+    {
+        _data = .;
+        *(.data*)
+        . = ALIGN (8);
+        _edata = .;
+    } > SRAM
+
+    .bss :
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        _ebss = .;
+    } > SRAM
+
+    .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :
+    {
+        . = ALIGN(8);
+        _stack = .;
+        . = . + __stack_size__;
+        . = ALIGN(8);
+        _estack = .;
+    } > SRAM
+}
+

cc3200/bootmgr/flc.h

@@ -0,0 +1,96 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __FLC_H__
+#define __FLC_H__
+
+/******************************************************************************
+
+   If building with a C++ compiler, make all of the definitions in this header
+   have a C binding.
+  
+*******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+   Image file names
+*******************************************************************************/
+#define IMG_BOOT_INFO           "/sys/bootinfo.bin"
+#define IMG_FACTORY             "/sys/factimg.bin"
+#define IMG_UPDATE1             "/sys/updtimg1.bin"
+#define IMG_UPDATE2             "/sys/updtimg2.bin"
+#define IMG_PREFIX              "/sys/updtimg"
+
+#define IMG_SRVPACK             "/sys/servicepack.ucf"
+#define SRVPACK_SIGN            "/sys/servicepack.sig"
+
+#define CA_FILE                 "/cert/ca.pem"
+#define CERT_FILE               "/cert/cert.pem"
+#define KEY_FILE                "/cert/private.key"
+
+/******************************************************************************
+   Special file sizes
+*******************************************************************************/
+#define IMG_SIZE                (192 * 1024)    /* 16KB are reserved for the bootloader and at least 48KB for the heap*/
+#define SRVPACK_SIZE            (16  * 1024)
+#define SIGN_SIZE               (2   * 1024)
+#define CA_KEY_SIZE             (4   * 1024)
+
+/******************************************************************************
+   Active Image
+*******************************************************************************/
+#define IMG_ACT_FACTORY         0
+#define IMG_ACT_UPDATE1         1
+#define IMG_ACT_UPDATE2         2
+
+#define IMG_STATUS_CHECK        0
+#define IMG_STATUS_READY        1
+
+/******************************************************************************
+   Boot Info structure
+*******************************************************************************/
+typedef struct _sBootInfo_t
+{
+  _u8  ActiveImg;
+  _u8  Status;
+  _u8  PrevImg;
+  _u8  : 8;
+} sBootInfo_t;
+
+
+/******************************************************************************
+  
+   Mark the end of the C bindings section for C++ compilers.
+  
+*******************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FLC_H__ */

cc3200/bootmgr/main.c

@@ -0,0 +1,420 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "std.h"
+
+#include "py/mpconfig.h"
+#include "hw_ints.h"
+#include "hw_types.h"
+#include "hw_gpio.h"
+#include "hw_memmap.h"
+#include "hw_gprcm.h"
+#include "hw_common_reg.h"
+#include "pin.h"
+#include "gpio.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "simplelink.h"
+#include "interrupt.h"
+#include "gpio.h"
+#include "flc.h"
+#include "bootmgr.h"
+#include "shamd5.h"
+#include "cryptohash.h"
+#include "utils.h"
+#include "cc3200_hal.h"
+#include "debug.h"
+#include "mperror.h"
+#include "antenna.h"
+
+
+//*****************************************************************************
+// Local Constants
+//*****************************************************************************
+#define SL_STOP_TIMEOUT                     35
+#define BOOTMGR_HASH_ALGO                   SHAMD5_ALGO_MD5
+#define BOOTMGR_HASH_SIZE                   32
+#define BOOTMGR_BUFF_SIZE                   512
+
+#define BOOTMGR_WAIT_SAFE_MODE_0_MS         500
+
+#define BOOTMGR_WAIT_SAFE_MODE_1_MS         3000
+#define BOOTMGR_WAIT_SAFE_MODE_1_BLINK_MS   500
+
+#define BOOTMGR_WAIT_SAFE_MODE_2_MS         3000
+#define BOOTMGR_WAIT_SAFE_MODE_2_BLINK_MS   250
+
+#define BOOTMGR_WAIT_SAFE_MODE_3_MS         1500
+#define BOOTMGR_WAIT_SAFE_MODE_3_BLINK_MS   100
+
+//*****************************************************************************
+// Exported functions declarations
+//*****************************************************************************
+extern void bootmgr_run_app (_u32 base);
+
+//*****************************************************************************
+// Local functions declarations
+//*****************************************************************************
+static void bootmgr_board_init (void);
+static bool bootmgr_verify (_u8 *image);
+static void bootmgr_load_and_execute (_u8 *image);
+static bool wait_while_blinking (uint32_t wait_time, uint32_t period, bool force_wait);
+static bool safe_boot_request_start (uint32_t wait_time);
+static void wait_for_safe_boot (sBootInfo_t *psBootInfo);
+static void bootmgr_image_loader (sBootInfo_t *psBootInfo);
+
+//*****************************************************************************
+// Private data
+//*****************************************************************************
+static _u8 bootmgr_file_buf[BOOTMGR_BUFF_SIZE];
+static _u8 bootmgr_hash_buf[BOOTMGR_HASH_SIZE + 1];
+
+//*****************************************************************************
+// Vector Table
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+
+//*****************************************************************************
+// WLAN Event handler callback hookup function
+//*****************************************************************************
+void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent)
+{
+
+}
+
+//*****************************************************************************
+// HTTP Server callback hookup function
+//*****************************************************************************
+void SimpleLinkHttpServerCallback(SlHttpServerEvent_t *pHttpEvent,
+                                  SlHttpServerResponse_t *pHttpResponse)
+{
+
+}
+
+//*****************************************************************************
+// Net APP Event callback hookup function
+//*****************************************************************************
+void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent)
+{
+
+}
+
+//*****************************************************************************
+// General Event callback hookup function
+//*****************************************************************************
+void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent)
+{
+
+}
+
+//*****************************************************************************
+// Socket Event callback hookup function
+//*****************************************************************************
+void SimpleLinkSockEventHandler(SlSockEvent_t *pSock)
+{
+
+}
+
+//*****************************************************************************
+//! Board Initialization & Configuration
+//*****************************************************************************
+static void bootmgr_board_init(void) {
+    // set the vector table base
+    MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]);
+
+    // enable processor interrupts
+    MAP_IntMasterEnable();
+    MAP_IntEnable(FAULT_SYSTICK);
+
+    // mandatory MCU initialization
+    PRCMCC3200MCUInit();
+
+    // clear all the special bits, since we can't trust their content after reset
+    // except for the WDT reset one!!
+    PRCMClearSpecialBit(PRCM_SAFE_BOOT_BIT);
+    PRCMClearSpecialBit(PRCM_FIRST_BOOT_BIT);
+
+    // check the reset after clearing the special bits
+    mperror_bootloader_check_reset_cause();
+
+#if MICROPY_HW_ANTENNA_DIVERSITY
+    // configure the antenna selection pins
+    antenna_init0();
+#endif
+
+    // enable the data hashing engine
+    CRYPTOHASH_Init();
+
+    // init the system led and the system switch
+    mperror_init0();
+}
+
+//*****************************************************************************
+//! Verifies the integrity of the new application binary
+//*****************************************************************************
+static bool bootmgr_verify (_u8 *image) {
+    SlFsFileInfo_t FsFileInfo;
+    _u32 reqlen, offset = 0;
+    _i32 fHandle;
+
+    // open the file for reading
+    if (0 == sl_FsOpen(image, FS_MODE_OPEN_READ, NULL, &fHandle)) {
+        // get the file size
+        sl_FsGetInfo(image, 0, &FsFileInfo);
+
+        if (FsFileInfo.FileLen > BOOTMGR_HASH_SIZE) {
+            FsFileInfo.FileLen -= BOOTMGR_HASH_SIZE;
+            CRYPTOHASH_SHAMD5Start(BOOTMGR_HASH_ALGO, FsFileInfo.FileLen);
+            do {
+                if ((FsFileInfo.FileLen - offset) > BOOTMGR_BUFF_SIZE) {
+                    reqlen = BOOTMGR_BUFF_SIZE;
+                }
+                else {
+                    reqlen = FsFileInfo.FileLen - offset;
+                }
+
+                offset += sl_FsRead(fHandle, offset, bootmgr_file_buf, reqlen);
+                CRYPTOHASH_SHAMD5Update(bootmgr_file_buf, reqlen);
+            } while (offset < FsFileInfo.FileLen);
+
+            CRYPTOHASH_SHAMD5Read (bootmgr_file_buf);
+
+            // convert the resulting hash to hex
+            for (_u32 i = 0; i < (BOOTMGR_HASH_SIZE / 2); i++) {
+                snprintf ((char *)&bootmgr_hash_buf[(i * 2)], 3, "%02x", bootmgr_file_buf[i]);
+            }
+
+            // read the hash from the file and close it
+            sl_FsRead(fHandle, offset, bootmgr_file_buf, BOOTMGR_HASH_SIZE);
+            sl_FsClose (fHandle, NULL, NULL, 0);
+            bootmgr_file_buf[BOOTMGR_HASH_SIZE] = '\0';
+            // compare both hashes
+            if (!strcmp((const char *)bootmgr_hash_buf, (const char *)bootmgr_file_buf)) {
+                // it's a match
+                return true;
+            }
+        }
+        // close the file
+        sl_FsClose(fHandle, NULL, NULL, 0);
+    }
+    return false;
+}
+
+//*****************************************************************************
+//! Loads the application from sFlash and executes
+//*****************************************************************************
+static void bootmgr_load_and_execute (_u8 *image) {
+    SlFsFileInfo_t pFsFileInfo;
+    _i32 fhandle;
+    // open the application binary
+    if (!sl_FsOpen(image, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+        // get the file size
+        if (!sl_FsGetInfo(image, 0, &pFsFileInfo)) {
+            // read the application into SRAM
+            if (pFsFileInfo.FileLen == sl_FsRead(fhandle, 0, (unsigned char *)APP_IMG_SRAM_OFFSET, pFsFileInfo.FileLen)) {
+                // close the file
+                sl_FsClose(fhandle, 0, 0, 0);
+                // stop the network services
+                sl_Stop(SL_STOP_TIMEOUT);
+                // execute the application
+                bootmgr_run_app(APP_IMG_SRAM_OFFSET);
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//! Wait while the safe mode pin is being held high and blink the system led
+//! with the specified period
+//*****************************************************************************
+static bool wait_while_blinking (uint32_t wait_time, uint32_t period, bool force_wait) {
+    _u32 count;
+    for (count = 0; (force_wait || MAP_GPIOPinRead(MICROPY_SAFE_BOOT_PORT, MICROPY_SAFE_BOOT_PORT_PIN)) &&
+         ((period * count) < wait_time); count++) {
+        // toogle the led
+        MAP_GPIOPinWrite(MICROPY_SYS_LED_PORT, MICROPY_SYS_LED_PORT_PIN, ~MAP_GPIOPinRead(MICROPY_SYS_LED_PORT, MICROPY_SYS_LED_PORT_PIN));
+        UtilsDelay(UTILS_DELAY_US_TO_COUNT(period * 1000));
+    }
+    return MAP_GPIOPinRead(MICROPY_SAFE_BOOT_PORT, MICROPY_SAFE_BOOT_PORT_PIN) ? true : false;
+}
+
+static bool safe_boot_request_start (uint32_t wait_time) {
+    if (MAP_GPIOPinRead(MICROPY_SAFE_BOOT_PORT, MICROPY_SAFE_BOOT_PORT_PIN)) {
+        UtilsDelay(UTILS_DELAY_US_TO_COUNT(wait_time * 1000));
+    }
+    return MAP_GPIOPinRead(MICROPY_SAFE_BOOT_PORT, MICROPY_SAFE_BOOT_PORT_PIN) ? true : false;
+}
+
+//*****************************************************************************
+//! Check for the safe mode pin
+//*****************************************************************************
+static void wait_for_safe_boot (sBootInfo_t *psBootInfo) {
+    if (safe_boot_request_start(BOOTMGR_WAIT_SAFE_MODE_0_MS)) {
+        if (wait_while_blinking(BOOTMGR_WAIT_SAFE_MODE_1_MS, BOOTMGR_WAIT_SAFE_MODE_1_BLINK_MS, false)) {
+            // go back one step in time
+            psBootInfo->ActiveImg = psBootInfo->PrevImg;
+            if (wait_while_blinking(BOOTMGR_WAIT_SAFE_MODE_2_MS, BOOTMGR_WAIT_SAFE_MODE_2_BLINK_MS, false)) {
+                // go back directly to the factory image
+                psBootInfo->ActiveImg = IMG_ACT_FACTORY;
+                wait_while_blinking(BOOTMGR_WAIT_SAFE_MODE_3_MS, BOOTMGR_WAIT_SAFE_MODE_3_BLINK_MS, true);
+            }
+        }
+        // turn off the system led
+        MAP_GPIOPinWrite(MICROPY_SYS_LED_PORT, MICROPY_SYS_LED_PORT_PIN, 0);
+        // request a safe boot to the application
+        PRCMSetSpecialBit(PRCM_SAFE_BOOT_BIT);
+    }
+    // deinit the safe boot pin
+    mperror_deinit_sfe_pin();
+}
+
+//*****************************************************************************
+//! Load the proper image based on the information from the boot info
+//! and launch it.
+//*****************************************************************************
+static void bootmgr_image_loader(sBootInfo_t *psBootInfo) {
+    _i32 fhandle;
+    _u8 *image;
+
+    // search for the active image
+    switch (psBootInfo->ActiveImg) {
+    case IMG_ACT_UPDATE1:
+        image = (unsigned char *)IMG_UPDATE1;
+        break;
+    case IMG_ACT_UPDATE2:
+        image = (unsigned char *)IMG_UPDATE2;
+        break;
+    default:
+        image = (unsigned char *)IMG_FACTORY;
+        break;
+    }
+
+    // do we have a new image that needs to be verified?
+    if ((psBootInfo->ActiveImg != IMG_ACT_FACTORY) && (psBootInfo->Status == IMG_STATUS_CHECK)) {
+        if (!bootmgr_verify(image)) {
+            // verification failed, delete the broken file
+            sl_FsDel(image, 0);
+            // switch to the previous image
+            psBootInfo->ActiveImg = psBootInfo->PrevImg;
+            psBootInfo->PrevImg = IMG_ACT_FACTORY;
+        }
+        // in any case, change the status to "READY"
+        psBootInfo->Status = IMG_STATUS_READY;
+        // write the new boot info
+        if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_WRITE, NULL, &fhandle)) {
+            sl_FsWrite(fhandle, 0, (unsigned char *)psBootInfo, sizeof(sBootInfo_t));
+            // close the file
+            sl_FsClose(fhandle, 0, 0, 0);
+        }
+    }
+
+    // this one might modify the boot info hence it MUST be called after
+    // bootmgr_verify! (so that the changes are not saved to flash)
+    wait_for_safe_boot(psBootInfo);
+
+    // select the active image again, since it might have changed
+    switch (psBootInfo->ActiveImg) {
+    case IMG_ACT_UPDATE1:
+        image = (unsigned char *)IMG_UPDATE1;
+        break;
+    case IMG_ACT_UPDATE2:
+        image = (unsigned char *)IMG_UPDATE2;
+        break;
+    default:
+        image = (unsigned char *)IMG_FACTORY;
+        break;
+    }
+    bootmgr_load_and_execute(image);
+}
+
+//*****************************************************************************
+//! Main function
+//*****************************************************************************
+int main (void) {
+    sBootInfo_t sBootInfo = { .ActiveImg = IMG_ACT_FACTORY, .Status = IMG_STATUS_READY, .PrevImg = IMG_ACT_FACTORY };
+    bool bootapp = false;
+    _i32 fhandle;
+
+    // board setup
+    bootmgr_board_init();
+
+    // start simplelink since we need it to access the sflash
+    sl_Start(0, 0, 0);
+
+    // if a boot info file is found, load it, else, create a new one with the default boot info
+    if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+        if (sizeof(sBootInfo_t) == sl_FsRead(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t))) {
+            bootapp = true;
+        }
+        sl_FsClose(fhandle, 0, 0, 0);
+    }
+    // boot info file not present, it means that this is the first boot after being programmed
+    if (!bootapp) {
+        // create a new boot info file
+        _u32 BootInfoCreateFlag  = _FS_FILE_OPEN_FLAG_COMMIT | _FS_FILE_PUBLIC_WRITE | _FS_FILE_PUBLIC_READ;
+        if (!sl_FsOpen ((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_CREATE((2 * sizeof(sBootInfo_t)),
+                        BootInfoCreateFlag), NULL, &fhandle)) {
+            // write the default boot info.
+            if (sizeof(sBootInfo_t) == sl_FsWrite(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t))) {
+                bootapp = true;
+            }
+            sl_FsClose(fhandle, 0, 0, 0);
+        }
+        // signal the first boot to the application
+        PRCMSetSpecialBit(PRCM_FIRST_BOOT_BIT);
+    }
+
+    if (bootapp) {
+        // load and execute the image based on the boot info
+        bootmgr_image_loader(&sBootInfo);
+    }
+
+    // stop simplelink
+    sl_Stop(SL_STOP_TIMEOUT);
+
+    // if we've reached this point, then it means that a fatal error has occurred and the
+    // application could not be loaded, so, loop forever and signal the crash to the user
+    while (true) {
+        // keep the bld on
+        MAP_GPIOPinWrite(MICROPY_SYS_LED_PORT, MICROPY_SYS_LED_PORT_PIN, MICROPY_SYS_LED_PORT_PIN);
+        __asm volatile(" dsb \n"
+                       " isb \n"
+                       " wfi \n");
+    }
+}
+
+//*****************************************************************************
+//! The following stub function is needed to link mp_vprintf
+//*****************************************************************************
+#include "py/qstr.h"
+
+const byte *qstr_data(qstr q, size_t *len) {
+    *len = 0;
+    return NULL;
+}

cc3200/bootmgr/runapp.s

@@ -0,0 +1,19 @@
+    .syntax unified
+    .cpu cortex-m4
+    .thumb
+    .text
+    .align  2
+
+@ void bootmgr_run_app(_u32 base)
+    .global bootmgr_run_app
+    .thumb
+    .thumb_func
+    .type   bootmgr_run_app, %function
+bootmgr_run_app:
+    @ set the SP
+    ldr    sp, [r0]
+    add    r0, r0, #4
+
+    @ jump to the entry code
+    ldr    r1, [r0]
+    bx     r1

cc3200/fatfs/src/diskio.c

@@ -0,0 +1,209 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2014        */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various exsisting      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "py/mpconfig.h"
+#include "py/runtime.h"
+#include "py/obj.h"
+#include "lib/fatfs/ff.h"
+#include "lib/fatfs/diskio.h"   /* FatFs lower layer API */
+#include "sflash_diskio.h"      /* Serial flash disk IO API */
+#include "sd_diskio.h"          /* SDCARD disk IO API */
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "pybrtc.h"
+#include "timeutils.h"
+#include "pybsd.h"
+#include "moduos.h"
+
+
+/*-----------------------------------------------------------------------*/
+/* Get Drive Status                                                      */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive nmuber to identify the drive */
+)
+{
+    if (pdrv == PD_FLASH) {
+        return sflash_disk_status();
+    } else {
+        os_fs_mount_t *mount_obj;
+        if ((mount_obj = osmount_find_by_volume(pdrv))) {
+            if (mount_obj->writeblocks[0] == MP_OBJ_NULL) {
+                return STA_PROTECT;
+            }
+            return 0;
+        }
+    }
+    return STA_NODISK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive                                                    */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+    if (pdrv == PD_FLASH) {
+        if (RES_OK != sflash_disk_init()) {
+            return STA_NOINIT;
+        }
+    } else {
+        os_fs_mount_t *mount_obj;
+        if ((mount_obj = osmount_find_by_volume(pdrv))) {
+            if (mount_obj->writeblocks[0] == MP_OBJ_NULL) {
+                return STA_PROTECT;
+            }
+            return 0;
+        }
+    }
+    return STA_NODISK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s)                                                        */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	DWORD sector,	/* Sector address in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+    if (pdrv == PD_FLASH) {
+        return sflash_disk_read(buff, sector, count);
+    } else {
+        os_fs_mount_t *mount_obj;
+        if ((mount_obj = osmount_find_by_volume(pdrv))) {
+            // optimization for the built-in sd card device
+            if (mount_obj->device == (mp_obj_t)&pybsd_obj) {
+                return sd_disk_read(buff, sector, count);
+            }
+            mount_obj->readblocks[2] = MP_OBJ_NEW_SMALL_INT(sector);
+            mount_obj->readblocks[3] = mp_obj_new_bytearray_by_ref(count * 512, buff);
+            return mp_obj_get_int(mp_call_method_n_kw(2, 0, mount_obj->readblocks));
+        }
+        // nothing mounted
+        return RES_ERROR;
+    }
+    return RES_PARERR;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s)                                                       */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_WRITE
+DRESULT disk_write (
+	BYTE pdrv,			/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	DWORD sector,		/* Sector address in LBA */
+	UINT count			/* Number of sectors to write */
+)
+{
+    if (pdrv == PD_FLASH) {
+        return sflash_disk_write(buff, sector, count);
+    } else {
+        os_fs_mount_t *mount_obj;
+        if ((mount_obj = osmount_find_by_volume(pdrv))) {
+            // optimization for the built-in sd card device
+            if (mount_obj->device == (mp_obj_t)&pybsd_obj) {
+                return sd_disk_write(buff, sector, count);
+            }
+            mount_obj->writeblocks[2] = MP_OBJ_NEW_SMALL_INT(sector);
+            mount_obj->writeblocks[3] = mp_obj_new_bytearray_by_ref(count * 512, (void *)buff);
+            return mp_obj_get_int(mp_call_method_n_kw(2, 0, mount_obj->writeblocks));
+        }
+        // nothing mounted
+        return RES_ERROR;
+    }
+    return RES_PARERR;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions                                               */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_IOCTL
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+    if (pdrv == PD_FLASH) {
+        switch (cmd) {
+        case CTRL_SYNC:
+            return sflash_disk_flush();
+        case GET_SECTOR_COUNT:
+            *((DWORD*)buff) = SFLASH_SECTOR_COUNT;
+            return RES_OK;
+        case GET_SECTOR_SIZE:
+            *((DWORD*)buff) = SFLASH_SECTOR_SIZE;
+            return RES_OK;
+        case GET_BLOCK_SIZE:
+            *((DWORD*)buff) = 1; // high-level sector erase size in units of the block size
+            return RES_OK;
+        }
+    } else {
+        os_fs_mount_t *mount_obj;
+        if ((mount_obj = osmount_find_by_volume(pdrv))) {
+            switch (cmd) {
+            case CTRL_SYNC:
+                if (mount_obj->sync[0] != MP_OBJ_NULL) {
+                    mp_call_method_n_kw(0, 0, mount_obj->sync);
+                }
+                return RES_OK;
+            case GET_SECTOR_COUNT:
+                // optimization for the built-in sd card device
+                if (mount_obj->device == (mp_obj_t)&pybsd_obj) {
+                    *((DWORD*)buff) = sd_disk_info.ulNofBlock * (sd_disk_info.ulBlockSize / 512);
+                } else {
+                    *((DWORD*)buff) = mp_obj_get_int(mp_call_method_n_kw(0, 0, mount_obj->count));
+                }
+                return RES_OK;
+            case GET_SECTOR_SIZE:
+                *((DWORD*)buff) = SD_SECTOR_SIZE;  // Sector size is fixed to 512 bytes, as with SD cards
+                return RES_OK;
+            case GET_BLOCK_SIZE:
+                *((DWORD*)buff) = 1; // high-level sector erase size in units of the block size
+                return RES_OK;
+            }
+        }
+        // nothing mounted
+        return RES_ERROR;
+    }
+    return RES_PARERR;
+}
+#endif
+
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (
+    void
+)
+{
+    timeutils_struct_time_t tm;
+    timeutils_seconds_since_2000_to_struct_time(pyb_rtc_get_seconds(), &tm);
+
+    return ((tm.tm_year - 1980) << 25) | ((tm.tm_mon) << 21)  |
+            ((tm.tm_mday) << 16)       | ((tm.tm_hour) << 11) |
+            ((tm.tm_min) << 5)         | (tm.tm_sec >> 1);
+}
+#endif
+

cc3200/fatfs/src/drivers/sd_diskio.c

@@ -0,0 +1,432 @@
+//*****************************************************************************
+// sd_diskio.c
+//
+// Low level SD Card access hookup for FatFS
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+#include <stdbool.h>
+
+#include "py/mpconfig.h"
+#include "py/mphal.h"
+#include "hw_types.h"
+#include "hw_memmap.h"
+#include "hw_ints.h"
+#include "rom_map.h"
+#include "diskio.h"
+#include "sd_diskio.h"
+#include "sdhost.h"
+#include "pin.h"
+#include "prcm.h"
+#include "stdcmd.h"
+#include "utils.h"
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define DISKIO_RETRY_TIMEOUT        0xFFFFFFFF
+
+#define CARD_TYPE_UNKNOWN           0
+#define CARD_TYPE_MMC               1
+#define CARD_TYPE_SDCARD            2
+
+#define CARD_CAP_CLASS_SDSC         0
+#define CARD_CAP_CLASS_SDHC         1
+
+#define CARD_VERSION_1              0
+#define CARD_VERSION_2              1
+
+//*****************************************************************************
+// Disk Info for attached disk
+//*****************************************************************************
+DiskInfo_t sd_disk_info =  {CARD_TYPE_UNKNOWN, CARD_VERSION_1, CARD_CAP_CLASS_SDSC, 0, 0, STA_NOINIT, 0};
+
+//*****************************************************************************
+//
+//! Send Command to card
+//!
+//! \param ulCmd is the command to be send
+//! \paran ulArg is the command argument
+//!
+//! This function sends command to attached card and check the response status
+//! if any.
+//!
+//! \return Returns 0 on success, 1 otherwise
+//
+//*****************************************************************************
+static unsigned int CardSendCmd (unsigned int ulCmd, unsigned int ulArg) {
+    unsigned long ulStatus;
+
+    // Clear the interrupt status
+    MAP_SDHostIntClear(SDHOST_BASE,0xFFFFFFFF);
+
+    // Send command
+    MAP_SDHostCmdSend(SDHOST_BASE,ulCmd,ulArg);
+
+    // Wait for command complete or error
+    do {
+        ulStatus = MAP_SDHostIntStatus(SDHOST_BASE);
+        ulStatus = (ulStatus & (SDHOST_INT_CC | SDHOST_INT_ERRI));
+    } while (!ulStatus);
+
+    // Check error status
+    if (ulStatus & SDHOST_INT_ERRI) {
+        // Reset the command line
+        MAP_SDHostCmdReset(SDHOST_BASE);
+        return 1;
+    }
+    else {
+        return 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! Get the capacity of specified card
+//!
+//! \param ulRCA is the Relative Card Address (RCA)
+//!
+//! This function gets the capacity of card addressed by \e ulRCA paramaeter.
+//!
+//! \return Returns 0 on success, 1 otherwise.
+//
+//*****************************************************************************
+static unsigned int CardCapacityGet(DiskInfo_t *psDiskInfo) {
+    unsigned long ulRet;
+    unsigned long ulResp[4];
+    unsigned long ulBlockSize;
+    unsigned long ulBlockCount;
+    unsigned long ulCSizeMult;
+    unsigned long ulCSize;
+
+    // Read the CSD register
+    ulRet = CardSendCmd(CMD_SEND_CSD, (psDiskInfo->usRCA << 16));
+
+    if(ulRet == 0) {
+        // Read the response
+        MAP_SDHostRespGet(SDHOST_BASE,ulResp);
+
+        // 136 bit CSD register is read into an array of 4 words.
+        // ulResp[0] = CSD[31:0]
+        // ulResp[1] = CSD[63:32]
+        // ulResp[2] = CSD[95:64]
+        // ulResp[3] = CSD[127:96]
+        if(ulResp[3] >> 30) {
+            ulBlockSize = SD_SECTOR_SIZE * 1024;
+            ulBlockCount = (ulResp[1] >> 16 | ((ulResp[2] & 0x3F) << 16)) + 1;
+        }
+        else {
+            ulBlockSize  = 1 << ((ulResp[2] >> 16) & 0xF);
+            ulCSizeMult  = ((ulResp[1] >> 15) & 0x7);
+            ulCSize      = ((ulResp[1] >> 30) | (ulResp[2] & 0x3FF) << 2);
+            ulBlockCount = (ulCSize + 1) * (1 << (ulCSizeMult + 2));
+        }
+
+        // Calculate the card capacity in bytes
+        psDiskInfo->ulBlockSize = ulBlockSize;
+        psDiskInfo->ulNofBlock  = ulBlockCount;
+    }
+
+    return ulRet;
+}
+
+//*****************************************************************************
+//
+//! Select a card for reading or writing
+//!
+//! \param Card is the pointer to card attribute structure.
+//!
+//! This function selects a card for reading or writing using its RCA from
+//! \e Card parameter.
+//!
+//! \return Returns 0 success, 1 otherwise.
+//
+//*****************************************************************************
+static unsigned int CardSelect (DiskInfo_t *sDiskInfo) {
+    unsigned long ulRCA;
+    unsigned long ulRet;
+
+    ulRCA = sDiskInfo->usRCA;
+
+    // Send select command with card's RCA.
+    ulRet = CardSendCmd(CMD_SELECT_CARD, (ulRCA << 16));
+
+    if (ulRet == 0) {
+        while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+    }
+
+    // Delay 250ms for the card to become ready
+    mp_hal_delay_ms(250);
+
+    return ulRet;
+}
+
+//*****************************************************************************
+//
+//! Initializes physical drive
+//!
+//! This function initializes the physical drive
+//!
+//! \return Returns 0 on succeeded.
+//*****************************************************************************
+DSTATUS sd_disk_init (void) {
+    unsigned long ulRet;
+    unsigned long ulResp[4];
+
+    if (sd_disk_info.bStatus != 0) {
+        sd_disk_info.bStatus = STA_NODISK;
+        // Send std GO IDLE command
+        if (CardSendCmd(CMD_GO_IDLE_STATE, 0) == 0) {
+            // Get interface operating condition for the card
+            ulRet = CardSendCmd(CMD_SEND_IF_COND,0x000001A5);
+            MAP_SDHostRespGet(SDHOST_BASE,ulResp);
+
+            // It's a SD ver 2.0 or higher card
+            if (ulRet == 0 && ((ulResp[0] & 0xFF) == 0xA5)) {
+                // Version 1 card do not respond to this command
+                sd_disk_info.ulVersion = CARD_VERSION_2;
+                sd_disk_info.ucCardType = CARD_TYPE_SDCARD;
+
+                // Wait for card to become ready.
+                do {
+                    // Send ACMD41
+                    CardSendCmd(CMD_APP_CMD, 0);
+                    ulRet = CardSendCmd(CMD_SD_SEND_OP_COND, 0x40E00000);
+
+                    // Response contains 32-bit OCR register
+                    MAP_SDHostRespGet(SDHOST_BASE, ulResp);
+
+                } while (((ulResp[0] >> 31) == 0));
+
+                if (ulResp[0] & (1UL<<30)) {
+                    sd_disk_info.ulCapClass = CARD_CAP_CLASS_SDHC;
+                }
+                sd_disk_info.bStatus = 0;
+            }
+            //It's a MMC or SD 1.x card
+            else {
+                // Wait for card to become ready.
+                do {
+                    CardSendCmd(CMD_APP_CMD, 0);
+                    ulRet = CardSendCmd(CMD_SD_SEND_OP_COND,0x00E00000);
+                    if (ulRet == 0) {
+                        // Response contains 32-bit OCR register
+                        MAP_SDHostRespGet(SDHOST_BASE, ulResp);
+                    }
+                } while (((ulRet == 0) && (ulResp[0] >> 31) == 0));
+
+                if (ulRet == 0) {
+                    sd_disk_info.ucCardType = CARD_TYPE_SDCARD;
+                    sd_disk_info.bStatus = 0;
+                }
+                else {
+                    if (CardSendCmd(CMD_SEND_OP_COND, 0) == 0) {
+                        // MMC not supported by the controller
+                        sd_disk_info.ucCardType = CARD_TYPE_MMC;
+                    }
+                }
+            }
+        }
+
+        // Get the RCA of the attached card
+        if (sd_disk_info.bStatus == 0) {
+            ulRet = CardSendCmd(CMD_ALL_SEND_CID, 0);
+            if (ulRet == 0) {
+                CardSendCmd(CMD_SEND_REL_ADDR,0);
+                MAP_SDHostRespGet(SDHOST_BASE, ulResp);
+
+                //  Fill in the RCA
+                sd_disk_info.usRCA = (ulResp[0] >> 16);
+
+                // Get tha card capacity
+                CardCapacityGet(&sd_disk_info);
+            }
+
+            // Select the card.
+            ulRet = CardSelect(&sd_disk_info);
+            if (ulRet == 0) {
+                sd_disk_info.bStatus = 0;
+            }
+        }
+    }
+
+    return sd_disk_info.bStatus;
+}
+
+//*****************************************************************************
+//
+//! De-initializes the physical drive
+//!
+//! This function de-initializes the physical drive
+//*****************************************************************************
+void sd_disk_deinit (void) {
+    sd_disk_info.ucCardType = CARD_TYPE_UNKNOWN;
+    sd_disk_info.ulVersion = CARD_VERSION_1;
+    sd_disk_info.ulCapClass = CARD_CAP_CLASS_SDSC;
+    sd_disk_info.ulNofBlock = 0;
+    sd_disk_info.ulBlockSize = 0;
+    sd_disk_info.bStatus = STA_NOINIT;
+    sd_disk_info.usRCA = 0;
+}
+
+//*****************************************************************************
+//
+//! Reads sector(s) from the disk drive.
+//!
+//!
+//! This function reads specified number of sectors from the drive
+//!
+//! \return Returns RES_OK on success.
+//
+//*****************************************************************************
+DRESULT sd_disk_read (BYTE* pBuffer, DWORD ulSectorNumber, UINT SectorCount) {
+    DRESULT Res = RES_ERROR;
+    unsigned long ulSize;
+
+    if (SectorCount > 0) {
+        // Return if disk not initialized
+        if (sd_disk_info.bStatus & STA_NOINIT) {
+            return RES_NOTRDY;
+        }
+
+        // SDSC uses linear address, SDHC uses block address
+        if (sd_disk_info.ulCapClass == CARD_CAP_CLASS_SDSC) {
+            ulSectorNumber = ulSectorNumber * SD_SECTOR_SIZE;
+        }
+
+        // Set the block count
+        MAP_SDHostBlockCountSet(SDHOST_BASE, SectorCount);
+
+        // Compute the number of words
+        ulSize = (SD_SECTOR_SIZE * SectorCount) / 4;
+
+        // Check if 1 block or multi block transfer
+        if (SectorCount == 1) {
+            // Send single block read command
+            if (CardSendCmd(CMD_READ_SINGLE_BLK, ulSectorNumber) == 0) {
+                // Read the block of data
+                while (ulSize--) {
+                    MAP_SDHostDataRead(SDHOST_BASE, (unsigned long *)pBuffer);
+                    pBuffer += 4;
+                }
+                Res = RES_OK;
+            }
+        }
+        else {
+            // Send multi block read command
+            if (CardSendCmd(CMD_READ_MULTI_BLK, ulSectorNumber) == 0) {
+                // Read the data
+                while (ulSize--) {
+                    MAP_SDHostDataRead(SDHOST_BASE, (unsigned long *)pBuffer);
+                    pBuffer += 4;
+                }
+                CardSendCmd(CMD_STOP_TRANS, 0);
+                while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+                Res = RES_OK;
+            }
+        }
+    }
+
+    return Res;
+}
+
+//*****************************************************************************
+//
+//! Wrties sector(s) to the disk drive.
+//!
+//!
+//! This function writes specified number of sectors to the drive
+//!
+//! \return Returns RES_OK on success.
+//
+//*****************************************************************************
+DRESULT sd_disk_write (const BYTE* pBuffer, DWORD ulSectorNumber, UINT SectorCount) {
+    DRESULT Res = RES_ERROR;
+    unsigned long ulSize;
+
+    if (SectorCount > 0) {
+        // Return if disk not initialized
+        if (sd_disk_info.bStatus & STA_NOINIT) {
+            return RES_NOTRDY;
+        }
+
+        // SDSC uses linear address, SDHC uses block address
+        if (sd_disk_info.ulCapClass == CARD_CAP_CLASS_SDSC) {
+            ulSectorNumber = ulSectorNumber * SD_SECTOR_SIZE;
+        }
+
+        // Set the block count
+        MAP_SDHostBlockCountSet(SDHOST_BASE, SectorCount);
+
+        // Compute the number of words
+        ulSize = (SD_SECTOR_SIZE * SectorCount) / 4;
+
+        // Check if 1 block or multi block transfer
+        if (SectorCount == 1) {
+            // Send single block write command
+            if (CardSendCmd(CMD_WRITE_SINGLE_BLK, ulSectorNumber) == 0) {
+                // Write the data
+                while (ulSize--) {
+                    MAP_SDHostDataWrite (SDHOST_BASE, (*(unsigned long *)pBuffer));
+                    pBuffer += 4;
+                }
+                // Wait for data transfer complete
+                while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+                Res = RES_OK;
+            }
+        }
+        else {
+            // Set the card write block count
+            if (sd_disk_info.ucCardType == CARD_TYPE_SDCARD) {
+                CardSendCmd(CMD_APP_CMD,sd_disk_info.usRCA << 16);
+                CardSendCmd(CMD_SET_BLK_CNT, SectorCount);
+            }
+
+            // Send multi block write command
+            if (CardSendCmd(CMD_WRITE_MULTI_BLK, ulSectorNumber) == 0) {
+                // Write the data buffer
+                while (ulSize--) {
+                    MAP_SDHostDataWrite(SDHOST_BASE, (*(unsigned long *)pBuffer));
+                    pBuffer += 4;
+                }
+                // Wait for transfer complete
+                while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+                CardSendCmd(CMD_STOP_TRANS, 0);
+                while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+                Res = RES_OK;
+            }
+        }
+    }
+
+    return Res;
+}

cc3200/fatfs/src/drivers/sd_diskio.h

@@ -0,0 +1,27 @@
+#ifndef SD_DISKIO_H_
+#define SD_DISKIO_H_
+
+#define SD_SECTOR_SIZE          512
+
+//*****************************************************************************
+// Disk Info Structure definition
+//*****************************************************************************
+typedef struct
+{
+    unsigned char ucCardType;
+    unsigned int  ulVersion;
+    unsigned int  ulCapClass;
+    unsigned int ulNofBlock;
+    unsigned int ulBlockSize;
+    DSTATUS bStatus;
+    unsigned short usRCA;
+}DiskInfo_t;
+
+extern DiskInfo_t sd_disk_info;
+
+DSTATUS sd_disk_init (void);
+void sd_disk_deinit (void);
+DRESULT sd_disk_read (BYTE* pBuffer, DWORD ulSectorNumber, UINT bSectorCount);
+DRESULT sd_disk_write (const BYTE* pBuffer, DWORD ulSectorNumber, UINT bSectorCount);
+
+#endif /* SD_DISKIO_H_ */

cc3200/fatfs/src/drivers/sflash_diskio.c

@@ -0,0 +1,181 @@
+#include <stdint.h>
+#include <stdbool.h>
+#include "std.h"
+
+#include "py/mpconfig.h"
+#include "py/obj.h"
+#include "simplelink.h"
+#include "diskio.h"
+#include "sflash_diskio.h"
+#include "debug.h"
+#include "modnetwork.h"
+#include "modwlan.h"
+
+#define SFLASH_TIMEOUT_MAX_MS               5500
+#define SFLASH_WAIT_TIME_MS                 5
+
+static _u8 sflash_block_name[] =  "__NNN__.fsb";
+static _u8 *sflash_block_cache;
+static bool sflash_init_done = false;
+static bool sflash_cache_is_dirty;
+static uint32_t sflash_ublock;
+static uint32_t sflash_prblock;
+
+
+static void print_block_name (_u32 ublock) {
+    char _sblock[4];
+    snprintf (_sblock, sizeof(_sblock), "%03u", ublock);
+    memcpy (&sflash_block_name[2], _sblock, 3);
+}
+
+static bool sflash_access (_u32 mode, _i32 (* sl_FsFunction)(_i32 FileHdl, _u32 Offset, _u8* pData, _u32 Len)) {
+    _i32 fileHandle;
+    bool retval = false;
+
+    // wlan must be enabled in order to access the serial flash
+    sl_LockObjLock (&wlan_LockObj, SL_OS_WAIT_FOREVER);
+
+    if (0 == sl_FsOpen(sflash_block_name, mode, NULL, &fileHandle)) {
+        if (SFLASH_BLOCK_SIZE == sl_FsFunction (fileHandle, 0, sflash_block_cache, SFLASH_BLOCK_SIZE)) {
+            retval = true;
+        }
+        sl_FsClose (fileHandle, NULL, NULL, 0);
+    }
+    sl_LockObjUnlock (&wlan_LockObj);
+    return retval;
+}
+
+DRESULT sflash_disk_init (void) {
+    _i32 fileHandle;
+    SlFsFileInfo_t FsFileInfo;
+
+    if (!sflash_init_done) {
+        // Allocate space for the block cache
+        ASSERT ((sflash_block_cache = mem_Malloc(SFLASH_BLOCK_SIZE)) != NULL);
+        sflash_init_done = true;
+        sflash_prblock = UINT32_MAX;
+        sflash_cache_is_dirty = false;
+
+        // In order too speed up booting, check the last block, if exists, then
+        // it means that the file system has been already created
+        print_block_name (SFLASH_BLOCK_COUNT - 1);
+        sl_LockObjLock (&wlan_LockObj, SL_OS_WAIT_FOREVER);
+        if (!sl_FsGetInfo(sflash_block_name, 0, &FsFileInfo)) {
+            sl_LockObjUnlock (&wlan_LockObj);
+            return RES_OK;
+        }
+        sl_LockObjUnlock (&wlan_LockObj);
+
+        // Proceed to format the memory
+        for (int i = 0; i < SFLASH_BLOCK_COUNT; i++) {
+            print_block_name (i);
+            sl_LockObjLock (&wlan_LockObj, SL_OS_WAIT_FOREVER);
+            // Create the block file if it doesn't exist
+            if (sl_FsGetInfo(sflash_block_name, 0, &FsFileInfo) != 0) {
+                if (!sl_FsOpen(sflash_block_name, FS_MODE_OPEN_CREATE(SFLASH_BLOCK_SIZE, 0), NULL, &fileHandle)) {
+                    sl_FsClose(fileHandle, NULL, NULL, 0);
+                    sl_LockObjUnlock (&wlan_LockObj);
+                    memset(sflash_block_cache, 0xFF, SFLASH_BLOCK_SIZE);
+                    if (!sflash_access(FS_MODE_OPEN_WRITE, sl_FsWrite)) {
+                        return RES_ERROR;
+                    }
+                }
+                else {
+                    // Unexpected failure while creating the file
+                    sl_LockObjUnlock (&wlan_LockObj);
+                    return RES_ERROR;
+                }
+            }
+            sl_LockObjUnlock (&wlan_LockObj);
+        }
+    }
+    return RES_OK;
+}
+
+DRESULT sflash_disk_status(void) {
+    if (!sflash_init_done) {
+        return STA_NOINIT;
+    }
+    return RES_OK;
+}
+
+DRESULT sflash_disk_read(BYTE *buff, DWORD sector, UINT count) {
+    uint32_t secindex;
+
+    if (!sflash_init_done) {
+        return STA_NOINIT;
+    }
+
+    if ((sector + count > SFLASH_SECTOR_COUNT) || (count == 0)) {
+        return RES_PARERR;
+    }
+
+    for (int i = 0; i < count; i++) {
+        secindex = (sector + i) % SFLASH_SECTORS_PER_BLOCK;
+        sflash_ublock = (sector + i) / SFLASH_SECTORS_PER_BLOCK;
+        // See if it's time to read a new block
+        if (sflash_prblock != sflash_ublock) {
+            if (sflash_disk_flush() != RES_OK) {
+                return RES_ERROR;
+            }
+            sflash_prblock = sflash_ublock;
+            print_block_name (sflash_ublock);
+            if (!sflash_access(FS_MODE_OPEN_READ, sl_FsRead)) {
+                return RES_ERROR;
+            }
+        }
+        // Copy the requested sector from the block cache
+        memcpy (buff, &sflash_block_cache[(secindex * SFLASH_SECTOR_SIZE)], SFLASH_SECTOR_SIZE);
+        buff += SFLASH_SECTOR_SIZE;
+    }
+    return RES_OK;
+}
+
+DRESULT sflash_disk_write(const BYTE *buff, DWORD sector, UINT count) {
+    uint32_t secindex;
+    int32_t index = 0;
+
+    if (!sflash_init_done) {
+        return STA_NOINIT;
+    }
+
+    if ((sector + count > SFLASH_SECTOR_COUNT) || (count == 0)) {
+        sflash_disk_flush();
+        return RES_PARERR;
+    }
+
+    do {
+        secindex = (sector + index) % SFLASH_SECTORS_PER_BLOCK;
+        sflash_ublock = (sector + index) / SFLASH_SECTORS_PER_BLOCK;
+        // Check if it's a different block than last time
+        if (sflash_prblock != sflash_ublock) {
+            if (sflash_disk_flush() != RES_OK) {
+                return RES_ERROR;
+            }
+            sflash_prblock = sflash_ublock;
+            print_block_name (sflash_ublock);
+            // Read the block into the cache
+            if (!sflash_access(FS_MODE_OPEN_READ, sl_FsRead)) {
+                return RES_ERROR;
+            }
+        }
+        // Copy the input sector to the block cache
+        memcpy (&sflash_block_cache[(secindex * SFLASH_SECTOR_SIZE)], buff, SFLASH_SECTOR_SIZE);
+        buff += SFLASH_SECTOR_SIZE;
+        sflash_cache_is_dirty = true;
+    } while (++index < count);
+
+    return RES_OK;
+}
+
+DRESULT sflash_disk_flush (void) {
+    // Write back the cache if it's dirty
+    if (sflash_cache_is_dirty) {
+        if (!sflash_access(FS_MODE_OPEN_WRITE, sl_FsWrite)) {
+            return RES_ERROR;
+        }
+        sflash_cache_is_dirty = false;
+    }
+    return RES_OK;
+}
+

cc3200/fatfs/src/drivers/sflash_diskio.h

@@ -0,0 +1,16 @@
+#ifndef SFLASH_DISKIO_H_
+#define SFLASH_DISKIO_H_
+
+#define SFLASH_BLOCK_SIZE           2048
+#define SFLASH_BLOCK_COUNT          MICROPY_PORT_SFLASH_BLOCK_COUNT
+#define SFLASH_SECTOR_SIZE          512
+#define SFLASH_SECTOR_COUNT         ((SFLASH_BLOCK_SIZE * SFLASH_BLOCK_COUNT) / SFLASH_SECTOR_SIZE)
+#define SFLASH_SECTORS_PER_BLOCK    (SFLASH_BLOCK_SIZE / SFLASH_SECTOR_SIZE)
+
+DRESULT sflash_disk_init(void);
+DRESULT sflash_disk_status(void);
+DRESULT sflash_disk_read(BYTE *buff, DWORD sector, UINT count);
+DRESULT sflash_disk_write(const BYTE *buff, DWORD sector, UINT count);
+DRESULT sflash_disk_flush(void);
+
+#endif /* SFLASH_DISKIO_H_ */

cc3200/fatfs/src/drivers/stdcmd.h

@@ -0,0 +1,62 @@
+//*****************************************************************************
+// stdcmd.h
+//
+// Defines standard SD Card commands for CC3200 SDHOST module. 
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 
+// 
+// 
+//  Redistribution and use in source and binary forms, with or without 
+//  modification, are permitted provided that the following conditions 
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright 
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the 
+//    documentation and/or other materials provided with the   
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __STDCMD_H__
+#define __STDCMD_H__
+
+//*****************************************************************************
+// Standard MMC/SD Card Commands                           
+//*****************************************************************************
+#define CMD_GO_IDLE_STATE    SDHOST_CMD_0
+#define CMD_SEND_IF_COND     SDHOST_CMD_8|SDHOST_RESP_LEN_48
+#define CMD_SEND_CSD         SDHOST_CMD_9|SDHOST_RESP_LEN_136
+#define CMD_APP_CMD          SDHOST_CMD_55|SDHOST_RESP_LEN_48
+#define CMD_SD_SEND_OP_COND  SDHOST_CMD_41|SDHOST_RESP_LEN_48
+#define CMD_SEND_OP_COND     SDHOST_CMD_1|SDHOST_RESP_LEN_48
+#define CMD_READ_SINGLE_BLK  SDHOST_CMD_17|SDHOST_RD_CMD|SDHOST_RESP_LEN_48
+#define CMD_READ_MULTI_BLK   SDHOST_CMD_18|SDHOST_RD_CMD|SDHOST_RESP_LEN_48|SDHOST_MULTI_BLK
+#define CMD_WRITE_SINGLE_BLK SDHOST_CMD_24|SDHOST_WR_CMD|SDHOST_RESP_LEN_48
+#define CMD_WRITE_MULTI_BLK  SDHOST_CMD_25|SDHOST_WR_CMD|SDHOST_RESP_LEN_48|SDHOST_MULTI_BLK
+#define CMD_SELECT_CARD      SDHOST_CMD_7|SDHOST_RESP_LEN_48B
+#define CMD_DESELECT_CARD    SDHOST_CMD_7
+#define CMD_STOP_TRANS       SDHOST_CMD_12|SDHOST_RESP_LEN_48B
+#define CMD_SET_BLK_CNT      SDHOST_CMD_23|SDHOST_RESP_LEN_48
+#define CMD_ALL_SEND_CID     SDHOST_CMD_2|SDHOST_RESP_LEN_136
+#define CMD_SEND_REL_ADDR    SDHOST_CMD_3|SDHOST_RESP_LEN_48
+
+#endif //__STDCMD_H__

cc3200/fatfs/src/ffconf.c

@@ -0,0 +1,93 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <string.h>
+
+#include "py/mpstate.h"
+#include "lib/fatfs/ff.h"
+#include "lib/fatfs/ffconf.h"
+#include "lib/fatfs/diskio.h"
+#include "moduos.h"
+
+#if _FS_RPATH
+extern BYTE ff_CurrVol;
+#endif
+
+STATIC bool check_path(const TCHAR **path, const char *mount_point_str, mp_uint_t mount_point_len) {
+    if (strncmp(*path, mount_point_str, mount_point_len) == 0) {
+        if ((*path)[mount_point_len] == '/') {
+            *path += mount_point_len;
+            return true;
+        } else if ((*path)[mount_point_len] == '\0') {
+            *path = "/";
+            return true;
+        }
+    }
+    return false;
+}
+
+// "path" is the path to lookup; will advance this pointer beyond the volume name.
+// Returns logical drive number (-1 means invalid path).
+int ff_get_ldnumber (const TCHAR **path) {
+    if (!(*path)) {
+        return -1;
+    }
+
+    if (**path != '/') {
+    #if _FS_RPATH
+        return ff_CurrVol;
+    #else
+        return -1;
+    #endif
+    }
+
+    if (check_path(path, "/flash", 6)) {
+        return PD_FLASH;
+    }
+    else {
+        for (mp_uint_t i = 0; i < MP_STATE_PORT(mount_obj_list).len; i++) {
+            os_fs_mount_t *mount_obj = ((os_fs_mount_t *)(MP_STATE_PORT(mount_obj_list).items[i]));
+            if (check_path(path, mount_obj->path, mount_obj->pathlen)) {
+                return mount_obj->vol;
+            }
+        }
+    }
+
+    return -1;
+}
+
+void ff_get_volname(BYTE vol, TCHAR **dest) {
+    if (vol == PD_FLASH) {
+        memcpy(*dest, "/flash", 6);
+        *dest += 6;
+    } else {
+        os_fs_mount_t *mount_obj;
+        if ((mount_obj = osmount_find_by_volume(vol))) {
+            memcpy(*dest, mount_obj->path, mount_obj->pathlen);
+            *dest += mount_obj->pathlen;
+        }
+    }
+}

cc3200/fatfs/src/option/syscall.c

@@ -0,0 +1,150 @@
+/*------------------------------------------------------------------------*/
+/* Sample code of OS dependent controls for FatFs                         */
+/* (C)ChaN, 2014                                                          */
+/*------------------------------------------------------------------------*/
+
+#include "ff.h"
+
+
+#if _FS_REENTRANT
+/*------------------------------------------------------------------------*/
+/* Create a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to create a new
+/  synchronization object, such as semaphore and mutex. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_cre_syncobj (	/* !=0:Function succeeded, ==0:Could not create due to any error */
+	BYTE vol,			/* Corresponding logical drive being processed */
+	_SYNC_t *sobj		/* Pointer to return the created sync object */
+)
+{
+	int ret;
+
+//
+//	*sobj = CreateMutex(NULL, FALSE, NULL);		/* Win32 */
+//	ret = (int)(*sobj != INVALID_HANDLE_VALUE);
+
+//	*sobj = SyncObjects[vol];			/* uITRON (give a static created sync object) */
+//	ret = 1;							/* The initial value of the semaphore must be 1. */
+
+//	*sobj = OSMutexCreate(0, &err);		/* uC/OS-II */
+//	ret = (int)(err == OS_NO_ERR);
+
+	vSemaphoreCreateBinary( (*sobj) );	/* FreeRTOS */
+	ret = (int)(*sobj != NULL);
+
+	return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to delete a synchronization
+/  object that created with ff_cre_syncobj function. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj (	/* !=0:Function succeeded, ==0:Could not delete due to any error */
+	_SYNC_t sobj		/* Sync object tied to the logical drive to be deleted */
+)
+{
+	int ret;
+
+
+//	ret = CloseHandle(sobj);	/* Win32 */
+
+//	ret = 1;					/* uITRON (nothing to do) */
+
+//	OSMutexDel(sobj, OS_DEL_ALWAYS, &err);	/* uC/OS-II */
+//	ret = (int)(err == OS_NO_ERR);
+
+    vSemaphoreDelete(sobj);		/* FreeRTOS */
+	ret = 1;
+
+	return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/  When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant (	/* 1:Got a grant to access the volume, 0:Could not get a grant */
+	_SYNC_t sobj	/* Sync object to wait */
+)
+{
+	int ret;
+
+//	ret = (int)(WaitForSingleObject(sobj, _FS_TIMEOUT) == WAIT_OBJECT_0);	/* Win32 */
+
+//	ret = (int)(wai_sem(sobj) == E_OK);			/* uITRON */
+
+//	OSMutexPend(sobj, _FS_TIMEOUT, &err));		/* uC/OS-II */
+//	ret = (int)(err == OS_NO_ERR);
+
+	ret = (int)(xSemaphoreTake(sobj, _FS_TIMEOUT) == pdTRUE);	/* FreeRTOS */
+
+	return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+	_SYNC_t sobj	/* Sync object to be signaled */
+)
+{
+//	ReleaseMutex(sobj);		/* Win32 */
+
+//	sig_sem(sobj);			/* uITRON */
+
+//	OSMutexPost(sobj);		/* uC/OS-II */
+
+	xSemaphoreGive(sobj);	/* FreeRTOS */
+}
+
+#endif
+
+
+
+
+#if _USE_LFN == 3	/* LFN with a working buffer on the heap */
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block                                                */
+/*------------------------------------------------------------------------*/
+/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
+*/
+
+void* ff_memalloc ( /* Returns pointer to the allocated memory block */
+    UINT msize      /* Number of bytes to allocate */
+)
+{
+    return pvPortMalloc(msize);   /* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block                                                    */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+    void* mblock    /* Pointer to the memory block to free */
+)
+{
+    vPortFree(mblock);   /* Discard the memory block with POSIX API */
+}
+
+#endif

cc3200/ftp/ftp.h

@@ -0,0 +1,39 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef FTP_H_
+#define FTP_H_
+
+/******************************************************************************
+ DECLARE EXPORTED FUNCTIONS
+ ******************************************************************************/
+extern void ftp_init (void);
+extern void ftp_run (void);
+extern void ftp_enable (void);
+extern void ftp_disable (void);
+extern void ftp_reset (void);
+
+#endif /* FTP_H_ */

cc3200/ftp/updater.c

@@ -0,0 +1,202 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "py/mpconfig.h"
+#include "py/obj.h"
+#include "simplelink.h"
+#include "flc.h"
+#include "updater.h"
+#include "shamd5.h"
+#include "modnetwork.h"
+#include "modwlan.h"
+#include "debug.h"
+#include "osi.h"
+
+/******************************************************************************
+ DEFINE PRIVATE CONSTANTS
+ ******************************************************************************/
+#define UPDATER_IMG_PATH            "/flash/sys/mcuimg.bin"
+#define UPDATER_SRVPACK_PATH        "/flash/sys/servicepack.ucf"
+#define UPDATER_SIGN_PATH           "/flash/sys/servicepack.sig"
+#define UPDATER_CA_PATH             "/flash/cert/ca.pem"
+#define UPDATER_CERT_PATH           "/flash/cert/cert.pem"
+#define UPDATER_KEY_PATH            "/flash/cert/private.key"
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+typedef struct {
+    char *path;
+    _i32 fhandle;
+    _u32 fsize;
+    _u32 foffset;
+} updater_data_t;
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+static updater_data_t updater_data = { .path = NULL, .fhandle = -1, .fsize = 0, .foffset = 0 };
+static OsiLockObj_t updater_LockObj;
+static sBootInfo_t sBootInfo;
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+__attribute__ ((section (".boot")))
+void updater_pre_init (void) {
+    // create the updater lock
+    ASSERT(OSI_OK == sl_LockObjCreate(&updater_LockObj, "UpdaterLock"));
+}
+
+bool updater_check_path (void *path) {
+    sl_LockObjLock (&updater_LockObj, SL_OS_WAIT_FOREVER);
+    if (!strcmp(UPDATER_IMG_PATH, path)) {
+        updater_data.fsize = IMG_SIZE;
+        updater_data.path = IMG_UPDATE1;
+// the launchxl doesn't have enough flash space for 2 user update images
+#ifdef WIPY
+        // check which one should be the next active image
+         _i32 fhandle;
+        if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+            ASSERT (sizeof(sBootInfo_t) == sl_FsRead(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t)));
+            sl_FsClose(fhandle, 0, 0, 0);
+            // if we still have an image pending for verification, keep overwriting it
+            if ((sBootInfo.Status == IMG_STATUS_CHECK && sBootInfo.ActiveImg == IMG_ACT_UPDATE2) ||
+                 (sBootInfo.ActiveImg == IMG_ACT_UPDATE1 && sBootInfo.Status != IMG_STATUS_CHECK)) {
+                updater_data.path = IMG_UPDATE2;
+            }
+        }
+#endif
+    } else if (!strcmp(UPDATER_SRVPACK_PATH, path)) {
+        updater_data.path = IMG_SRVPACK;
+        updater_data.fsize = SRVPACK_SIZE;
+    } else if (!strcmp(UPDATER_SIGN_PATH, path)) {
+        updater_data.path = SRVPACK_SIGN;
+        updater_data.fsize = SIGN_SIZE;
+    } else if (!strcmp(UPDATER_CA_PATH, path)) {
+        updater_data.path = CA_FILE;
+        updater_data.fsize = CA_KEY_SIZE;
+    } else if (!strcmp(UPDATER_CERT_PATH, path)) {
+        updater_data.path = CERT_FILE;
+        updater_data.fsize = CA_KEY_SIZE;
+    } else if (!strcmp(UPDATER_KEY_PATH, path)) {
+        updater_data.path = KEY_FILE;
+        updater_data.fsize = CA_KEY_SIZE;
+    } else {
+        sl_LockObjUnlock (&updater_LockObj);
+        return false;
+    }
+    return true;
+}
+
+bool updater_start (void) {
+    _u32 AccessModeAndMaxSize = FS_MODE_OPEN_WRITE;
+    SlFsFileInfo_t FsFileInfo;
+    bool result = false;
+
+    sl_LockObjLock (&wlan_LockObj, SL_OS_WAIT_FOREVER);
+    if (0 != sl_FsGetInfo((_u8 *)updater_data.path, 0, &FsFileInfo)) {
+        // file doesn't exist, create it
+        AccessModeAndMaxSize = FS_MODE_OPEN_CREATE(updater_data.fsize, 0);
+    }
+    if (!sl_FsOpen((_u8 *)updater_data.path, AccessModeAndMaxSize, NULL, &updater_data.fhandle)) {
+        updater_data.foffset = 0;
+        result = true;
+    }
+    sl_LockObjUnlock (&wlan_LockObj);
+    return result;
+}
+
+bool updater_write (uint8_t *buf, uint32_t len) {
+    bool result = false;
+
+    sl_LockObjLock (&wlan_LockObj, SL_OS_WAIT_FOREVER);
+    if (len == sl_FsWrite(updater_data.fhandle, updater_data.foffset, buf, len)) {
+        updater_data.foffset += len;
+        result = true;
+    }
+    sl_LockObjUnlock (&wlan_LockObj);
+
+    return result;
+}
+
+void updater_finnish (void) {
+    _i32 fhandle;
+
+    if (updater_data.fhandle > 0) {
+        sl_LockObjLock (&wlan_LockObj, SL_OS_WAIT_FOREVER);
+        // close the file being updated
+        sl_FsClose(updater_data.fhandle, NULL, NULL, 0);
+#ifdef WIPY
+        // if we still have an image pending for verification, leave the boot info as it is
+        if (!strncmp(IMG_PREFIX, updater_data.path, strlen(IMG_PREFIX)) && sBootInfo.Status != IMG_STATUS_CHECK) {
+#else
+        if (!strncmp(IMG_PREFIX, updater_data.path, strlen(IMG_PREFIX))) {
+#endif
+#ifdef DEBUG
+            if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+
+                ASSERT (sizeof(sBootInfo_t) == sl_FsRead(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t)));
+                sl_FsClose(fhandle, 0, 0, 0);
+#endif
+                // open the boot info file for writing
+                ASSERT (sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_WRITE, NULL, &fhandle) == 0);
+#ifdef DEBUG
+            }
+            else {
+                // the boot info file doesn't exist yet
+                _u32 BootInfoCreateFlag  = _FS_FILE_OPEN_FLAG_COMMIT | _FS_FILE_PUBLIC_WRITE | _FS_FILE_PUBLIC_READ;
+                ASSERT (sl_FsOpen ((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_CREATE((2 * sizeof(sBootInfo_t)),
+                                   BootInfoCreateFlag), NULL, &fhandle) == 0);
+            }
+#endif
+
+            // save the new boot info
+#ifdef WIPY
+            sBootInfo.PrevImg = sBootInfo.ActiveImg;
+            if (sBootInfo.ActiveImg == IMG_ACT_UPDATE1) {
+                sBootInfo.ActiveImg = IMG_ACT_UPDATE2;
+            } else {
+                sBootInfo.ActiveImg = IMG_ACT_UPDATE1;
+            }
+// the launchxl doesn't have enough flash space for 2 user updates
+#else
+            sBootInfo.PrevImg = IMG_ACT_FACTORY;
+            sBootInfo.ActiveImg = IMG_ACT_UPDATE1;
+#endif
+            sBootInfo.Status = IMG_STATUS_CHECK;
+            ASSERT (sizeof(sBootInfo_t) == sl_FsWrite(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t)));
+            sl_FsClose(fhandle, 0, 0, 0);
+        }
+        sl_LockObjUnlock (&wlan_LockObj);
+        updater_data.fhandle = -1;
+    }
+    sl_LockObjUnlock (&updater_LockObj);
+}
+

cc3200/ftp/updater.h

@@ -0,0 +1,38 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+#ifndef UPDATER_H_
+#define UPDATER_H_
+
+extern void updater_pre_init (void);
+extern bool updater_check_path (void *path);
+extern bool updater_start (void);
+extern bool updater_write (uint8_t *buf, uint32_t len);
+extern void updater_finnish (void);
+extern bool updater_verify (uint8_t *rbuff, uint8_t *hasbuff);
+
+#endif /* UPDATER_H_ */

cc3200/hal/adc.c

@@ -0,0 +1,692 @@
+//*****************************************************************************
+//
+//  adc.c
+//
+//  Driver for the ADC module.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ADC_Analog_to_Digital_Converter_api
+//! @{
+//
+//*****************************************************************************
+#include "inc/hw_types.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_adc.h"
+#include "inc/hw_apps_config.h"
+#include "interrupt.h"
+#include "adc.h"
+
+
+//*****************************************************************************
+//
+//! Enables the ADC
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function sets the ADC global enable
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCEnable(unsigned long ulBase)
+{
+  //
+  // Set the global enable bit in the control register.
+  //
+  HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1;
+}
+
+//*****************************************************************************
+//
+//! Disable the ADC
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function clears the ADC global enable
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCDisable(unsigned long ulBase)
+{
+  //
+  // Clear the global enable bit in the control register.
+  //
+  HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ;
+}
+
+//*****************************************************************************
+//
+//! Enables specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function enables specified ADC channel and configures the
+//! pin as analog pin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulCh;
+
+  ulCh =  (ulChannel == ADC_CH_0)? 0x02 :
+          (ulChannel == ADC_CH_1)? 0x04 :
+          (ulChannel == ADC_CH_2)? 0x08 : 0x10;
+
+  HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh;
+}
+
+//*****************************************************************************
+//
+//! Disables specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channelsber
+//!
+//! This function disables specified ADC channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulCh;
+
+  ulCh =  (ulChannel == ADC_CH_0)? 0x02 :
+          (ulChannel == ADC_CH_1)? 0x04 :
+          (ulChannel == ADC_CH_2)? 0x08 : 0x10;
+
+  HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh;
+}
+
+//*****************************************************************************
+//
+//! Enables and registers ADC interrupt handler for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//! \param pfnHandler is a pointer to the function to be called when the
+//! ADC channel interrupt occurs.
+//!
+//! This function enables and registers ADC interrupt handler for specified
+//! channel. Individual interrupt for each channel should be enabled using
+//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear
+//! the interrupt source.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
+                    void (*pfnHandler)(void))
+{
+  unsigned long ulIntNo;
+
+  //
+  // Get the interrupt number associted with the specified channel
+  //
+  ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
+            (ulChannel == ADC_CH_1)? INT_ADCCH1 :
+            (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
+
+  //
+  // Register the interrupt handler
+  //
+  IntRegister(ulIntNo,pfnHandler);
+
+  //
+  // Enable ADC interrupt
+  //
+  IntEnable(ulIntNo);
+}
+
+
+//*****************************************************************************
+//
+//! Disables and unregisters ADC interrupt handler for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function disables and unregisters ADC interrupt handler for specified
+//! channel. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulIntNo;
+
+  //
+  // Get the interrupt number associted with the specified channel
+  //
+  ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
+            (ulChannel == ADC_CH_1)? INT_ADCCH1 :
+            (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
+
+  //
+  // Disable ADC interrupt
+  //
+  IntDisable(ulIntNo);
+
+  //
+  // Unregister the interrupt handler
+  //
+  IntUnregister(ulIntNo);
+}
+
+//*****************************************************************************
+//
+//! Enables individual interrupt sources for specified channel
+//!
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated ADC interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//! - \b ADC_DMA_DONE for DMA done
+//! - \b ADC_FIFO_OVERFLOW for FIFO over flow
+//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow
+//! - \b ADC_FIFO_EMPTY for FIFO empty
+//! - \b ADC_FIFO_FULL for FIFO full
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
+                  unsigned long ulIntFlags)
+{
+  unsigned long ulOffset;
+  unsigned long ulDmaMsk;
+
+  //
+  // Enable DMA Done interrupt
+  //
+  if(ulIntFlags & ADC_DMA_DONE)
+  {
+     ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+                (ulChannel == ADC_CH_1)?0x00002000:
+                (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
+  }
+
+  ulIntFlags = ulIntFlags &  0x0F;
+  //
+  // Get the interrupt enable register offset for specified channel
+  //
+  ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
+
+  //
+  // Unmask the specified interrupts
+  //
+  HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf);
+}
+
+
+//*****************************************************************************
+//
+//! Disables individual interrupt sources for specified channel
+//!
+//!
+//! \param ulBase is the base address of the ADC.
+//! \param ulChannel is one of the valid ADC channels
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function disables the indicated ADC interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The parameters\e ulIntFlags and \e ulChannel should be as explained in
+//! ADCIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
+                  unsigned long ulIntFlags)
+{
+  unsigned long ulOffset;
+  unsigned long ulDmaMsk;
+
+  //
+  // Disable DMA Done interrupt
+  //
+  if(ulIntFlags & ADC_DMA_DONE)
+  {
+     ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+                (ulChannel == ADC_CH_1)?0x00002000:
+                (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
+  }
+
+  //
+  // Get the interrupt enable register offset for specified channel
+  //
+  ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
+
+  //
+  // Unmask the specified interrupts
+  //
+  HWREG(ulBase + ulOffset) &= ~ulIntFlags;
+}
+
+
+//*****************************************************************************
+//
+//! Gets the current channel interrupt status
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function returns the interrupt status of the specified ADC channel.
+//!
+//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
+//!
+//! \return Return the ADC channel interrupt status,  enumerated as a bit
+//! field of values described in ADCIntEnable()
+//
+//*****************************************************************************
+unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulOffset;
+  unsigned long ulDmaMsk;
+  unsigned long ulIntStatus;
+
+  //
+  // Get DMA Done interrupt status
+  //
+  ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+            (ulChannel == ADC_CH_1)?0x00002000:
+            (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+  ulIntStatus = HWREG(APPS_CONFIG_BASE +
+                     APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk;
+
+
+  //
+  // Get the interrupt enable register offset for specified channel
+  //
+  ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
+
+  //
+  // Read ADC interrupt status
+  //
+  ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf;
+
+  //
+  // Return the current interrupt status
+  //
+  return(ulIntStatus);
+}
+
+
+//*****************************************************************************
+//
+//! Clears the current channel interrupt sources
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears individual interrupt source for the specified
+//! ADC channel.
+//!
+//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
+                  unsigned long ulIntFlags)
+{
+  unsigned long ulOffset;
+  unsigned long ulDmaMsk;
+
+  //
+  // Clear DMA Done interrupt
+  //
+  if(ulIntFlags & ADC_DMA_DONE)
+  {
+     ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+                (ulChannel == ADC_CH_1)?0x00002000:
+                (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
+  }
+
+  //
+  // Get the interrupt enable register offset for specified channel
+  //
+  ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
+
+  //
+  // Clear the specified interrupts
+  //
+  HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE));
+}
+
+//*****************************************************************************
+//
+//! Enables the ADC DMA operation for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function enables the DMA operation for specified ADC channel
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulBitMask;
+
+  //
+  // Get the bit mask for enabling DMA for specified channel
+  //
+  ulBitMask = (ulChannel == ADC_CH_0)?0x01:
+              (ulChannel == ADC_CH_1)?0x04:
+              (ulChannel == ADC_CH_2)?0x10:0x40;
+
+  //
+  // Enable DMA request for the specified channel
+  //
+  HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask;
+}
+
+//*****************************************************************************
+//
+//! Disables the ADC DMA operation for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function disables the DMA operation for specified ADC channel
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulBitMask;
+
+  //
+  // Get the bit mask for disabling DMA for specified channel
+  //
+  ulBitMask = (ulChannel == ADC_CH_0)?0x01:
+              (ulChannel == ADC_CH_1)?0x04:
+              (ulChannel == ADC_CH_2)?0x10:0x40;
+
+  //
+  // Disable DMA request for the specified channel
+  //
+  HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask;
+}
+
+//*****************************************************************************
+//
+//! Configures the ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulValue is wrap arround value of the timer
+//!
+//! This function Configures the ADC internal timer. The ADC timer is a 17 bit
+//! used to timestamp the ADC data samples internally.
+//! User can read the timestamp along with the sample from the FIFO register(s).
+//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp
+//!
+//! The parameter \e ulValue can take any value between 0 - 2^17
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue)
+{
+  unsigned long ulReg;
+
+  //
+  // Read the currrent config
+  //
+  ulReg =  HWREG(ulBase + ADC_O_adc_timer_configuration);
+
+  //
+  // Mask and set timer count field
+  //
+  ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF));
+
+  //
+  // Set the timer count value
+  //
+  HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg;
+}
+
+//*****************************************************************************
+//
+//! Resets ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function resets 17-bit ADC internal timer
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerReset(unsigned long ulBase)
+{
+  //
+  // Reset the timer
+  //
+  HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24);
+}
+
+//*****************************************************************************
+//
+//! Enables ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function enables 17-bit ADC internal timer
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerEnable(unsigned long ulBase)
+{
+  //
+  // Enable the timer
+  //
+  HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25);
+}
+
+//*****************************************************************************
+//
+//! Disables ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function disables 17-bit ADC internal timer
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerDisable(unsigned long ulBase)
+{
+  //
+  // Disable the timer
+  //
+  HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function the current value of 17-bit ADC internal timer
+//!
+//! \returns Return the current value of ADC internal timer.
+//
+//*****************************************************************************
+unsigned long ADCTimerValueGet(unsigned long ulBase)
+{
+  return(HWREG(ulBase + ADC_O_adc_timer_current_count));
+}
+
+//*****************************************************************************
+//
+//! Gets the current FIFO level for specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels.
+//!
+//! This function returns the current FIFO level for specified ADC channel.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \returns Return the current FIFO level for specified channel
+//
+//*****************************************************************************
+unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulOffset;
+
+  //
+  // Get the fifo level register offset for specified channel
+  //
+  ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel;
+
+  //
+  // Return FIFO level
+  //
+  return(HWREG(ulBase + ulOffset) & 0x7);
+}
+
+//*****************************************************************************
+//
+//! Reads FIFO for specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels.
+//!
+//! This function returns one data sample from the channel fifo as specified by
+//! \e ulChannel parameter.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \returns Return one data sample from the channel fifo.
+//
+//*****************************************************************************
+unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel)
+{
+  unsigned long ulOffset;
+
+  //
+  // Get the fifo register offset for specified channel
+  //
+  ulOffset = ADC_O_channel0FIFODATA + ulChannel;
+
+  //
+  // Return FIFO level
+  //
+  return(HWREG(ulBase + ulOffset));
+}
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************

cc3200/hal/adc.h

@@ -0,0 +1,117 @@
+//*****************************************************************************
+//
+//  adc.h
+//
+//  Defines and Macros for the ADC.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+// Values that can be passed to APIs as ulChannel parameter
+//*****************************************************************************
+#define ADC_CH_0   0x00000000
+#define ADC_CH_1   0x00000008
+#define ADC_CH_2   0x00000010
+#define ADC_CH_3   0x00000018
+
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCIntEnable(), ADCIntDisable()
+// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus()
+//
+//*****************************************************************************
+#define ADC_DMA_DONE        0x00000010
+#define ADC_FIFO_OVERFLOW   0x00000008
+#define ADC_FIFO_UNDERFLOW  0x00000004
+#define ADC_FIFO_EMPTY      0x00000002
+#define ADC_FIFO_FULL       0x00000001
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void ADCEnable(unsigned long ulBase);
+extern void ADCDisable(unsigned long ulBase);
+extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel);
+extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel);
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
+                    void (*pfnHandler)(void));
+extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel);
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
+                  unsigned long ulIntFlags);
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
+                  unsigned long ulIntFlags);
+extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel);
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
+                  unsigned long ulIntFlags);
+extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel);
+extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel);
+extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue);
+extern void ADCTimerEnable(unsigned long ulBase);
+extern void ADCTimerDisable(unsigned long ulBase);
+extern void ADCTimerReset(unsigned long ulBase);
+extern unsigned long ADCTimerValueGet(unsigned long ulBase);
+extern unsigned char ADCFIFOLvlGet(unsigned long ulBase,
+                                   unsigned long ulChannel);
+extern unsigned long ADCFIFORead(unsigned long ulBase,
+                                   unsigned long ulChannel);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADC_H__
+

cc3200/hal/aes.h

@@ -0,0 +1,218 @@
+//*****************************************************************************
+//
+//  aes.h
+//
+//  Defines and Macros for the AES module.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_AES_H__
+#define __DRIVERLIB_AES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operation direction in the
+// ui32Config argument in the AESConfig function.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_DIR_ENCRYPT     0x00000004
+#define AES_CFG_DIR_DECRYPT     0x00000000
+
+//*****************************************************************************
+//
+// The following defines are used to specify the key size in the ui32Config
+// argument in the AESConfig function.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_KEY_SIZE_128BIT 0x00000008
+#define AES_CFG_KEY_SIZE_192BIT 0x00000010
+#define AES_CFG_KEY_SIZE_256BIT 0x00000018
+
+//*****************************************************************************
+//
+// The following defines are used to specify the mode of operation in the
+// ui32Config argument in the AESConfig function.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_MODE_M          0x2007fe60
+#define AES_CFG_MODE_ECB        0x00000000
+#define AES_CFG_MODE_CBC        0x00000020
+#define AES_CFG_MODE_CTR        0x00000040
+#define AES_CFG_MODE_ICM        0x00000200
+#define AES_CFG_MODE_CFB        0x00000400
+#define AES_CFG_MODE_XTS_TWEAKJL \
+                                0x00000800
+#define AES_CFG_MODE_XTS_K2IJL \
+                                0x00001000
+#define AES_CFG_MODE_XTS_K2ILJ0 \
+                                0x00001800
+#define AES_CFG_MODE_F8         0x00002000
+#define AES_CFG_MODE_F9         0x20004000
+#define AES_CFG_MODE_CBCMAC     0x20008000
+#define AES_CFG_MODE_GCM_HLY0ZERO \
+                                0x20010040
+#define AES_CFG_MODE_GCM_HLY0CALC \
+                                0x20020040
+#define AES_CFG_MODE_GCM_HY0CALC \
+                                0x20030040
+#define AES_CFG_MODE_CCM        0x20040040
+
+//*****************************************************************************
+//
+// The following defines are used to specify the counter width in the
+// ui32Config argument in the AESConfig function.  It is only required to
+// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CTR_WIDTH_32    0x00000000
+#define AES_CFG_CTR_WIDTH_64    0x00000080
+#define AES_CFG_CTR_WIDTH_96    0x00000100
+#define AES_CFG_CTR_WIDTH_128   0x00000180
+
+//*****************************************************************************
+//
+// The following defines are used to define the width of the length field for
+// CCM operation through the ui32Config argument in the AESConfig function.
+// This value is also known as L.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CCM_L_2         0x00080000
+#define AES_CFG_CCM_L_4         0x00180000
+#define AES_CFG_CCM_L_8         0x00380000
+
+//*****************************************************************************
+//
+// The following defines are used to define the length of the authentication
+// field for CCM operations through the ui32Config argument in the AESConfig
+// function.  This value is also known as M.  Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CCM_M_4         0x00400000
+#define AES_CFG_CCM_M_6         0x00800000
+#define AES_CFG_CCM_M_8         0x00c00000
+#define AES_CFG_CCM_M_10        0x01000000
+#define AES_CFG_CCM_M_12        0x01400000
+#define AES_CFG_CCM_M_14        0x01800000
+#define AES_CFG_CCM_M_16        0x01c00000
+
+//*****************************************************************************
+//
+// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
+// AESIntStatus functions.
+//
+//*****************************************************************************
+#define AES_INT_CONTEXT_IN      0x00000001
+#define AES_INT_CONTEXT_OUT     0x00000008
+#define AES_INT_DATA_IN         0x00000002
+#define AES_INT_DATA_OUT        0x00000004
+#define AES_INT_DMA_CONTEXT_IN  0x00010000
+#define AES_INT_DMA_CONTEXT_OUT 0x00020000
+#define AES_INT_DMA_DATA_IN     0x00040000
+#define AES_INT_DMA_DATA_OUT    0x00080000
+
+//*****************************************************************************
+//
+// Defines used when enabling and disabling DMA requests in the
+// AESEnableDMA and AESDisableDMA functions.
+//
+//*****************************************************************************
+#define AES_DMA_DATA_IN         0x00000040
+#define AES_DMA_DATA_OUT        0x00000020
+#define AES_DMA_CONTEXT_IN      0x00000080
+#define AES_DMA_CONTEXT_OUT     0x00000100
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key,
+                       uint32_t ui32Keysize);
+extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,
+                       uint32_t ui32Keysize);
+extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);
+extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
+extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata);
+extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);
+extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);
+extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
+                                   uint8_t ui8Length);
+extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
+                        uint8_t ui8Length);
+extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
+                                    uint8_t ui8Length);
+extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
+                         uint8_t ui8Length);
+extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
+                           uint8_t *pui8Dest,
+               uint32_t ui32Length);
+extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src,
+                       uint32_t ui32Length,
+            uint8_t *pui8Tag);
+extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src,
+                             uint8_t *pui8Dest, uint32_t ui32Length,
+                             uint8_t *pui8AuthSrc, uint32_t ui32AuthLength,
+                             uint8_t *pui8Tag);
+extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
+extern void AESIntUnregister(uint32_t ui32Base);
+extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __DRIVERLIB_AES_H__

cc3200/hal/cc3200_asm.h

@@ -0,0 +1,94 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef CC3200_ASM_H_
+#define CC3200_ASM_H_
+
+// We have inlined IRQ functions for efficiency (they are generally
+// 1 machine instruction).
+//
+// Note on IRQ state: you should not need to know the specific
+// value of the state variable, but rather just pass the return
+// value from disable_irq back to enable_irq.  If you really need
+// to know the machine-specific values, see irq.h.
+
+#ifndef __disable_irq
+#define __disable_irq() __asm__ volatile ("cpsid i");
+#endif
+
+#ifndef DEBUG
+__attribute__(( always_inline ))
+static inline void __WFI(void) {
+    __asm volatile ("    dsb      \n"
+                    "    isb      \n"
+                    "    wfi      \n");
+}
+#else
+// For some reason the debugger gets disconnected when entering any of the sleep modes
+__attribute__(( always_inline ))
+static inline void __WFI(void) {
+    __asm volatile ("    dsb      \n"
+                    "    isb      \n");
+}
+#endif
+
+__attribute__(( always_inline ))
+static inline uint32_t __get_PRIMASK(void) {
+    uint32_t result;
+    __asm volatile ("mrs %0, primask" : "=r" (result));
+    return(result);
+}
+
+__attribute__(( always_inline ))
+static inline void __set_PRIMASK(uint32_t priMask) {
+    __asm volatile ("msr primask, %0" : : "r" (priMask) : "memory");
+}
+
+__attribute__(( always_inline ))
+static inline uint32_t __get_BASEPRI(void) {
+    uint32_t result;
+    __asm volatile ("mrs %0, basepri" : "=r" (result));
+    return(result);
+}
+
+__attribute__(( always_inline ))
+static inline void __set_BASEPRI(uint32_t value) {
+    __asm volatile ("msr basepri, %0" : : "r" (value) : "memory");
+}
+
+__attribute__(( always_inline ))
+static inline void enable_irq(mp_uint_t state) {
+    __set_PRIMASK(state);
+}
+
+__attribute__(( always_inline ))
+static inline mp_uint_t disable_irq(void) {
+    mp_uint_t state = __get_PRIMASK();
+    __disable_irq();
+    return state;
+}
+
+#endif /* CC3200_ASM_H_ */

cc3200/hal/cc3200_hal.c

@@ -0,0 +1,218 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+ /******************************************************************************
+ IMPORTS
+ ******************************************************************************/
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+
+#include "py/mpstate.h"
+#include "py/mphal.h"
+#include "py/runtime.h"
+#include "py/objstr.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "hw_memmap.h"
+#include "rom_map.h"
+#include "interrupt.h"
+#include "systick.h"
+#include "prcm.h"
+#include "pin.h"
+#include "mpexception.h"
+#include "telnet.h"
+#include "pybuart.h"
+#include "utils.h"
+#include "irq.h"
+#include "moduos.h"
+
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+#ifndef USE_FREERTOS
+static void hal_TickInit (void);
+#endif
+
+/******************************************************************************
+ DECLARE LOCAL DATA
+ ******************************************************************************/
+static volatile uint32_t HAL_tickCount;
+
+/******************************************************************************
+ DECLARE IMPORTED DATA
+ ******************************************************************************/
+extern void (* const g_pfnVectors[256])(void);
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+__attribute__ ((section (".boot")))
+void HAL_SystemInit (void) {
+    MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]);
+
+    // in the case of a release image, these steps are already performed by
+    // the bootloader so we can skip it and gain some code space
+#ifdef DEBUG
+    MAP_IntMasterEnable();
+    PRCMCC3200MCUInit();
+#endif
+
+#ifndef USE_FREERTOS
+    hal_TickInit();
+#endif
+}
+
+void HAL_SystemDeInit (void) {
+}
+ 
+void HAL_IncrementTick(void) {
+    HAL_tickCount++;
+}
+
+mp_uint_t mp_hal_ticks_ms(void) {
+    return HAL_tickCount;
+}
+
+void mp_hal_delay_ms(mp_uint_t delay) {
+    // only if we are not within interrupt context and interrupts are enabled
+    if ((HAL_NVIC_INT_CTRL_REG & HAL_VECTACTIVE_MASK) == 0 && query_irq() == IRQ_STATE_ENABLED) {
+        MP_THREAD_GIL_EXIT();
+        #ifdef USE_FREERTOS
+            vTaskDelay (delay / portTICK_PERIOD_MS);
+        #else
+            uint32_t start = HAL_tickCount;
+            // wraparound of tick is taken care of by 2's complement arithmetic.
+            while (HAL_tickCount - start < delay) {
+                // enter sleep mode, waiting for (at least) the SysTick interrupt.
+                __WFI();
+            }
+        #endif
+        MP_THREAD_GIL_ENTER();
+    } else {
+        for (int ms = 0; ms < delay; ms++) {
+            UtilsDelay(UTILS_DELAY_US_TO_COUNT(1000));
+        }
+    }
+}
+
+NORETURN void mp_hal_raise(int errno) {
+    nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, mp_obj_new_int(errno)));
+}
+
+void mp_hal_set_interrupt_char (int c) {
+    mpexception_set_interrupt_char (c);
+}
+
+void mp_hal_stdout_tx_str(const char *str) {
+    mp_hal_stdout_tx_strn(str, strlen(str));
+}
+
+void mp_hal_stdout_tx_strn(const char *str, size_t len) {
+    if (MP_STATE_PORT(os_term_dup_obj)) {
+        if (MP_OBJ_IS_TYPE(MP_STATE_PORT(os_term_dup_obj)->stream_o, &pyb_uart_type)) {
+            uart_tx_strn(MP_STATE_PORT(os_term_dup_obj)->stream_o, str, len);
+        } else {
+            MP_STATE_PORT(os_term_dup_obj)->write[2] = mp_obj_new_str_of_type(&mp_type_str, (const byte *)str, len);
+            mp_call_method_n_kw(1, 0, MP_STATE_PORT(os_term_dup_obj)->write);
+        }
+    }
+    // and also to telnet
+    telnet_tx_strn(str, len);
+}
+
+void mp_hal_stdout_tx_strn_cooked (const char *str, size_t len) {
+    int32_t nslen = 0;
+    const char *_str = str;
+
+    for (int i = 0; i < len; i++) {
+        if (str[i] == '\n') {
+            mp_hal_stdout_tx_strn(_str, nslen);
+            mp_hal_stdout_tx_strn("\r\n", 2);
+            _str += nslen + 1;
+            nslen = 0;
+        } else {
+            nslen++;
+        }
+    }
+    if (_str < str + len) {
+        mp_hal_stdout_tx_strn(_str, nslen);
+    }
+}
+
+int mp_hal_stdin_rx_chr(void) {
+    for ( ;; ) {
+        // read telnet first
+        if (telnet_rx_any()) {
+            return telnet_rx_char();
+        } else if (MP_STATE_PORT(os_term_dup_obj)) { // then the stdio_dup
+            if (MP_OBJ_IS_TYPE(MP_STATE_PORT(os_term_dup_obj)->stream_o, &pyb_uart_type)) {
+                if (uart_rx_any(MP_STATE_PORT(os_term_dup_obj)->stream_o)) {
+                    return uart_rx_char(MP_STATE_PORT(os_term_dup_obj)->stream_o);
+                }
+            } else {
+                MP_STATE_PORT(os_term_dup_obj)->read[2] = mp_obj_new_int(1);
+                mp_obj_t data = mp_call_method_n_kw(1, 0, MP_STATE_PORT(os_term_dup_obj)->read);
+                // data len is > 0
+                if (mp_obj_is_true(data)) {
+                    mp_buffer_info_t bufinfo;
+                    mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ);
+                    return ((int *)(bufinfo.buf))[0];
+                }
+            }
+        }
+        mp_hal_delay_ms(1);
+    }
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+#ifndef USE_FREERTOS
+static void hal_TickInit (void) {
+    HAL_tickCount = 0;
+    MAP_SysTickIntRegister(HAL_IncrementTick);
+    MAP_IntEnable(FAULT_SYSTICK);
+    MAP_SysTickIntEnable();
+    MAP_SysTickPeriodSet(HAL_FCPU_HZ / HAL_SYSTICK_PERIOD_US);
+    // Force a reload of the SysTick counter register
+    HWREG(NVIC_ST_CURRENT) = 0;
+    MAP_SysTickEnable();
+}
+#endif
+

cc3200/hal/cc3200_hal.h

@@ -0,0 +1,68 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef CC3200_LAUNCHXL_HAL_CC3200_HAL_H_
+#define CC3200_LAUNCHXL_HAL_CC3200_HAL_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/******************************************************************************
+ DEFINE CONSTANTS
+ ******************************************************************************/
+
+#define HAL_FCPU_MHZ                        80U
+#define HAL_FCPU_HZ                         (1000000U * HAL_FCPU_MHZ)
+#define HAL_SYSTICK_PERIOD_US               1000U
+#define UTILS_DELAY_US_TO_COUNT(us)         (((us) * HAL_FCPU_MHZ) / 6)
+
+#define HAL_NVIC_INT_CTRL_REG               (*((volatile uint32_t *) 0xE000ED04 ) )
+#define HAL_VECTACTIVE_MASK                 (0x1FUL)
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+
+/******************************************************************************
+ DEFINE FUNCTION-LIKE MACROS
+ ******************************************************************************/
+
+#define HAL_INTRODUCE_SYNC_BARRIER() {                      \
+                                        __asm(" dsb \n"     \
+                                              " isb \n");   \
+                                     }
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+extern void HAL_SystemInit (void);
+extern void HAL_SystemDeInit (void);
+extern void HAL_IncrementTick(void);
+extern NORETURN void mp_hal_raise(int errno);
+extern void mp_hal_set_interrupt_char (int c);
+
+#endif /* CC3200_LAUNCHXL_HAL_CC3200_HAL_H_ */

cc3200/hal/cpu.c

@@ -0,0 +1,412 @@
+//*****************************************************************************
+//
+//  cpu.c
+//
+//  Instruction wrappers for special CPU instructions needed by the
+//  drivers.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUcpsid(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    dsb      \n"
+          "    isb      \n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    dsb      \n"
+          "    isb      \n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    dsb      \n"
+          "    isb      \n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUprimask(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUcpsie(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    dsb      \n"
+          "    isb      \n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    dsb      \n"
+          "    isb      \n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    dsb      \n"
+          "    isb      \n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(gcc)
+void __attribute__((naked))
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    dsb      \n"
+          "    isb      \n"
+          "    wfi      \n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    dsb      \n"
+          "    isb      \n"
+          "    wfi      \n");
+}
+#endif
+#if defined(ccs)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    dsb      \n"
+          "    isb      \n"
+          "    wfi      \n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(gcc)
+void __attribute__((naked))
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    dsb      \n"
+          "    isb      \n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    dsb      \n"
+          "    isb      \n");
+}
+#endif
+#if defined(ccs)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    dsb      \n"
+          "    isb      \n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUbasepriGet(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif

cc3200/hal/cpu.h

@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+//  cpu.h
+//
+//  Prototypes for the CPU instruction wrapper functions.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
+extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__

cc3200/hal/crc.c

@@ -0,0 +1,305 @@
+//*****************************************************************************
+//
+//  crc.c
+//
+//  Driver for the CRC module.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup CRC_Cyclic_Redundancy_Check_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_dthe.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "crc.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+//! Set the configuration of CRC functionality with the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32CRCConfig is the configuration of the CRC engine.
+//!
+//! This function configures the operation of the CRC engine within the EC
+//! module.  The configuration is specified with the \e ui32CRCConfig argument.
+//! It is the logical OR of any of the following options:
+//!
+//! CRC Initialization Value
+//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value
+//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s'
+//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s'
+//!
+//! Input Data Size
+//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits
+//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits
+//!
+//! Post Process Reverse/Inverse
+//! - \b EC_CRC_CFG_RESINV - Result inverse enable
+//! - \b EC_CRC_CFG_OBR - Output reverse enable
+//!
+//! Input Bit Reverse
+//! - \b EC_CRC_CFG_IBR - Bit reverse enable
+//!
+//! Endian Control
+//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
+//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word
+//!
+//! Operation Type
+//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005
+//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021
+//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
+//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
+//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DTHE_BASE);
+    ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
+           (ui32CRCConfig & CRC_CFG_INIT_0) ||
+           (ui32CRCConfig & CRC_CFG_INIT_1) ||
+           (ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
+           (ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
+           (ui32CRCConfig & CRC_CFG_RESINV) ||
+           (ui32CRCConfig & CRC_CFG_OBR) ||
+           (ui32CRCConfig & CRC_CFG_IBR) ||
+           (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
+           (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
+           (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
+
+    //
+    // Write the control register with the configuration.
+    //
+    HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig;
+}
+
+//*****************************************************************************
+//
+//! Write the seed value for CRC operations in the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32Seed is the seed value.
+//!
+//! This function writes the seed value for use with CRC operations in the
+//! EC module.  This value is the start value for CRC operations.  If this
+//! value is not written, then the residual seed from the previous operation
+//! is used as the starting value.
+//!
+//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is
+//! set with the CRCConfigSet() function.
+//
+//*****************************************************************************
+void
+CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DTHE_BASE);
+
+    //
+    // Write the seed value to the seed register.
+    //
+    HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed;
+}
+
+//*****************************************************************************
+//
+//! Write data into the EC module for CRC operations.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32Data is the data to be written.
+//!
+//! This function writes either 8 or 32 bits of data into the EC module for
+//! CRC operations.  The distinction between 8 and 32 bits of data is made
+//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag
+//! is set using the CRCConfigSet() function.
+//!
+//! When writing 8 bits of data, ensure the data is in the least signficant
+//! byte position.  The remaining bytes should be written with zero.  For
+//! example, when writing 0xAB, \e ui32Data should be 0x000000AB.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DTHE_BASE);
+
+    //
+    // Write the data
+    //
+    HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data;
+}
+
+//*****************************************************************************
+//
+//! Reads the result of a CRC operation in the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//!
+//! This function reads either the unmodified CRC result or the post
+//! processed CRC result from the EC module.  The post-processing options
+//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR
+//! parameters in the CRCConfigSet() function.
+//!
+//! \return The CRC result.
+//
+//*****************************************************************************
+uint32_t
+CRCResultRead(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DTHE_BASE);
+
+    //
+    // return value.
+    //
+    return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP));
+
+}
+
+//*****************************************************************************
+//
+//! Process data to generate a CRC with the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param puiDataIn is a pointer to an array of data that is processed.
+//! \param ui32DataLength is the number of data items that are processed
+//! to produce the CRC.
+//! \param ui32Config the config parameter to determine the CRC mode
+//!
+//! This function processes an array of data to produce a CRC result.
+//! This function takes the CRC mode as the parameter.
+//!
+//! The data in the array pointed to be \e pui32DataIn is either an array
+//! of bytes or an array or words depending on the selection of the input
+//! data size options \b EC_CRC_CFG_SIZE_8BIT and
+//! \b EC_CRC_CFG_SIZE_32BIT.
+//!
+//! This function returns either the unmodified CRC result or the
+//! post- processed CRC result from the EC module.  The post-processing
+//! options are selectable through \b EC_CRC_CFG_RESINV and
+//! \b EC_CRC_CFG_OBR parameters.
+//!
+//! \return The CRC result.
+//
+//*****************************************************************************
+uint32_t
+CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
+               uint32_t ui32DataLength, uint32_t ui32Config)
+{
+    uint8_t *pui8DataIn;
+    uint32_t *pui32DataIn;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DTHE_BASE);
+
+    //
+    // See if the CRC is operating in 8-bit or 32-bit mode.
+    //
+    if(ui32Config & DTHE_CRC_CTRL_SIZE)
+    {
+        //
+        // The CRC is operating in 8-bit mode, so create an 8-bit pointer to
+        // the data.
+        //
+        pui8DataIn = (uint8_t *)puiDataIn;
+
+        //
+        // Loop through the input data.
+        //
+        while(ui32DataLength--)
+        {
+            //
+            // Write the next data byte.
+            //
+            HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++;
+        }
+    }
+    else
+    {
+        //
+        // The CRC is operating in 32-bit mode, so loop through the input data.
+        //
+    	pui32DataIn = (uint32_t *)puiDataIn;
+        while(ui32DataLength--)
+        {
+            //
+            // Write the next data word.
+            //
+            HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++;
+        }
+    }
+
+    //
+    // Return the result.
+    //
+    return(CRCResultRead(ui32Base));
+}
+
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************

cc3200/hal/crc.h

@@ -0,0 +1,98 @@
+//*****************************************************************************
+//
+//  crc.h
+//
+//  Defines and Macros for CRC module.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CRC_H__
+#define __DRIVERLIB_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used in the ui32Config argument of the
+// ECConfig function.
+//
+//*****************************************************************************
+#define CRC_CFG_INIT_SEED       0x00000000  // Initialize with seed
+#define CRC_CFG_INIT_0          0x00004000  // Initialize to all '0s'
+#define CRC_CFG_INIT_1          0x00006000  // Initialize to all '1s'
+#define CRC_CFG_SIZE_8BIT       0x00001000  // Input Data Size
+#define CRC_CFG_SIZE_32BIT      0x00000000  // Input Data Size
+#define CRC_CFG_RESINV          0x00000200  // Result Inverse Enable
+#define CRC_CFG_OBR             0x00000100  // Output Reverse Enable
+#define CRC_CFG_IBR             0x00000080  // Bit reverse enable
+#define CRC_CFG_ENDIAN_SBHW     0x00000000  // Swap byte in half-word
+#define CRC_CFG_ENDIAN_SHW      0x00000010  // Swap half-word
+#define CRC_CFG_TYPE_P8005      0x00000000  // Polynomial 0x8005
+#define CRC_CFG_TYPE_P1021      0x00000001  // Polynomial 0x1021
+#define CRC_CFG_TYPE_P4C11DB7   0x00000002  // Polynomial 0x4C11DB7
+#define CRC_CFG_TYPE_P1EDC6F41  0x00000003  // Polynomial 0x1EDC6F41
+#define CRC_CFG_TYPE_TCPCHKSUM  0x00000008  // TCP checksum
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
+extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
+               uint32_t ui32DataLength, uint32_t ui32Config);
+extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
+extern uint32_t CRCResultRead(uint32_t ui32Base);
+extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CRC_H__

cc3200/hal/debug.h

@@ -0,0 +1,63 @@
+//*****************************************************************************
+//
+//  debug.h
+//
+//  Macros for assisting debug of the driver library.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+#include "assert.h"
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#if defined(DEBUG) && !defined(BOOTLOADER)
+#define ASSERT(expr)        assert(expr)
+#else
+#define ASSERT(expr)        (void)(expr)
+#endif
+
+#endif // __DEBUG_H__

cc3200/hal/des.c

@@ -0,0 +1,887 @@
+//*****************************************************************************
+//
+//  des.c
+//
+//  Driver for the DES data transformation.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup DES_Data_Encryption_Standard_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "inc/hw_des.h"
+#include "inc/hw_dthe.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "debug.h"
+#include "des.h"
+#include "interrupt.h"
+
+
+//*****************************************************************************
+//
+//! Configures the DES module for operation.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Config is the configuration of the DES module.
+//!
+//! This function configures the DES module for operation.
+//!
+//! The \e ui32Config parameter is a bit-wise OR of a number of configuration
+//! flags. The valid flags are grouped below based on their function.
+//!
+//! The direction of the operation is specified with one of the following two
+//! flags.  Only one is permitted.
+//!
+//! - \b DES_CFG_DIR_ENCRYPT - Encryption
+//! - \b DES_CFG_DIR_DECRYPT - Decryption
+//!
+//! The operational mode of the DES engine is specified with one of the
+//! following flags. Only one is permitted.
+//!
+//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode
+//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode
+//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode
+//!
+//! The selection of single DES or triple DES is specified with one of the
+//! following two flags. Only one is permitted.
+//!
+//! - \b DES_CFG_SINGLE - Single DES
+//! - \b DES_CFG_TRIPLE - Triple DES
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Backup the save context field.
+    //
+    ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT);
+
+    //
+    // Write the control register.
+    //
+    HWREG(ui32Base + DES_O_CTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the key used for DES operations.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Key is a pointer to an array that holds the key
+//!
+//! This function sets the key used for DES operations.
+//!
+//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or
+//! 192 bits (6 words) if triple DES is being used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESKeySet(uint32_t ui32Base, uint8_t *pui8Key)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Write the first part of the key.
+    //
+    HWREG(ui32Base + DES_O_KEY1_L) =  * ((uint32_t *)(pui8Key + 0));
+    HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4));
+
+    //
+    // If we are performing triple DES, then write the key registers for
+    // the second and third rounds.
+    //
+    if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE)
+    {
+        HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8));
+        HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12));
+        HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16));
+        HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the initialization vector in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to
+//! be written into the initialization vectors registers.
+//!
+//! This function sets the initialization vector in the DES module.  It returns
+//! true if the registers were successfully written.  If the context registers
+//! cannot be written at the time the function was called, then false is
+//! returned.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Check to see if context registers can be overwritten.  If not, return
+    // false.
+    //
+    if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0)
+    {
+        return(false);
+    }
+
+    //
+    // Write the initialization vector registers.
+    //
+    HWREG(ui32Base + DES_O_IV_L) =  *((uint32_t *) (pui8IVdata + 0));
+    HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4));
+
+    //
+    // Return true to indicate the write was successful.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Sets the crytographic data length in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Length is the length of the data in bytes.
+//!
+//! This function writes the cryptographic data length into the DES module.
+//! When this register is written, the engine is triggersed to start using
+//! this context.
+//!
+//! \note Data lengths up to (2^32 - 1) bytes are allowed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Write the length register.
+    //
+    HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Dest is a pointer to an array of 2 words.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function returns true if the data was ready when the function was
+//! called. If the data was not ready, false is returned.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
+{
+	volatile uint32_t pui32Dest[2];
+	uint8_t ui8BytCnt;
+	uint8_t *pui8DestTemp;
+
+	//
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    if((ui8Length == 0)||(ui8Length>8))
+    {
+       	return(false);
+    }
+
+    //
+    // Check to see if the data is ready to be read.
+    //
+    if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+    {
+        return(false);
+    }
+
+    //
+    // Read two words of data from the data registers.
+    //
+    pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
+    pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
+
+    //
+    //Copy the data to a block memory
+    //
+    pui8DestTemp = (uint8_t *)pui32Dest;
+    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+    {
+ 		*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
+    }
+
+    //
+    // Return true to indicate a successful write.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers with blocking.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Dest is a pointer to an array of bytes.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function waits until the DES module is finished and encrypted or
+//! decrypted data is ready.  The output data is then stored in the pui8Dest
+//! array.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
+{
+	volatile uint32_t pui32Dest[2];
+	uint8_t ui8BytCnt;
+	uint8_t *pui8DestTemp;
+
+	//
+	// Check the arguments.
+	//
+	ASSERT(ui32Base == DES_BASE);
+	if((ui8Length == 0)||(ui8Length>8))
+	{
+		return;
+	}
+    //
+    // Wait for data output to be ready.
+    //
+    while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0)
+    {
+    }
+
+    //
+    // Read two words of data from the data registers.
+    //
+    pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
+    pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
+
+    //
+    //Copy the data to a block memory
+    //
+    pui8DestTemp = (uint8_t *)pui32Dest;
+    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+    {
+    	*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
+    }
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Src is a pointer to an array of 2 words.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function returns false if the DES module is not ready to accept
+//! data.  It returns true if the data was written successfully.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
+{
+
+    volatile uint32_t pui32Src[2]={0,0};
+    uint8_t ui8BytCnt;
+    uint8_t *pui8SrcTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    if((ui8Length == 0)||(ui8Length>8))
+    {
+            return(false);
+    }
+
+    //
+    // Check if the DES module is ready to encrypt or decrypt data.  If it
+    // is not, return false.
+    //
+    if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))))
+    {
+        return(false);
+    }
+
+    //
+    // Copy the data to a block memory
+    //
+    pui8SrcTemp = (uint8_t *)pui32Src;
+    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+    {
+            *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
+    }
+
+    //
+    // Write the data.
+    //
+    HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
+    HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
+
+    //
+    // Return true to indicate a successful write.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Src is a pointer to an array of bytes.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function waits until the DES module is ready before writing the
+//! data contained in the pui8Src array.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
+{
+    volatile uint32_t pui32Src[2]={0,0};
+    uint8_t ui8BytCnt;
+    uint8_t *pui8SrcTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    if((ui8Length == 0)||(ui8Length>8))
+    {
+            return;
+    }
+
+    //
+    // Wait for the input ready bit to go high.
+    //
+    while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0)
+    {
+    }
+
+    //
+    //Copy the data to a block memory
+    //
+    pui8SrcTemp = (uint8_t *)pui32Src;
+    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+    {
+            *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
+    }
+
+    //
+    // Write the data.
+    //
+    HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
+    HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
+}
+
+//*****************************************************************************
+//
+//! Processes blocks of data through the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Src is a pointer to an array of words that contains the
+//! source data for processing.
+//! \param pui8Dest is a pointer to an array of words consisting of the
+//! processed data.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//! It must be a multiple of eight.
+//!
+//! This function takes the data contained in the pui8Src array and processes
+//! it using the DES engine.  The resulting data is stored in the
+//! pui8Dest array.  The function blocks until all of the data has been
+//! processed. If processing is successful, the function returns true.
+//!
+//! \note This functions assumes that the DES module has been configured,
+//! and initialization values and keys have been written.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
+               uint32_t ui32Length)
+{
+    uint32_t ui32Count, ui32BlkCount, ui32ByteCount;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32Length % 8) == 0);
+
+    //
+    // Write the length register first. This triggers the engine to start
+    // using this context.
+    //
+    HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
+
+
+    //
+    // Now loop until the blocks are written.
+    //
+    ui32BlkCount = ui32Length/8;
+    for(ui32Count = 0; ui32Count <ui32BlkCount; ui32Count ++)
+    {
+      //
+      // Check if the input ready is fine
+      //
+      while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+      {
+      }
+
+      //
+      // Write the data registers.
+      //
+      DESDataWriteNonBlocking(ui32Base, pui8Src + ui32Count*8 ,8);
+
+      //
+      // Wait for the output ready
+      //
+      while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+      {
+      }
+
+      //
+      // Read the data registers.
+      //
+      DESDataReadNonBlocking(ui32Base, pui8Dest + ui32Count*8 ,8);
+    }
+
+    //
+    //Now handle the residue bytes
+    //
+    ui32ByteCount = ui32Length%8;
+    if(ui32ByteCount)
+    {
+      //
+      // Check if the input ready is fine
+      //
+      while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+      {
+      }
+      //
+      // Write the data registers.
+      //
+      DESDataWriteNonBlocking(ui32Base, pui8Src + (8*ui32BlkCount) ,
+                              ui32ByteCount);
+      //
+      // Wait for the output ready
+      //
+      while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+      {
+      }
+
+      //
+      // Read the data registers.
+      //
+      DESDataReadNonBlocking(ui32Base, pui8Dest + (8*ui32BlkCount) ,
+                             ui32ByteCount);
+    }
+
+
+
+    //
+    // Return true to indicate the process was successful.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Returns the current interrupt status of the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function gets the current interrupt status of the DES module.
+//! The value returned is a logical OR of the following values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT_INT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return A bit mask of the current interrupt status.
+//
+//*****************************************************************************
+uint32_t
+DESIntStatus(uint32_t ui32Base, bool bMasked)
+{
+   uint32_t ui32IntStatus;
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Read the status register and return the value.
+    //
+    if(bMasked)
+    {
+        ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);
+        ui32IntStatus &= HWREG(ui32Base + DES_O_IRQENABLE);
+        ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0x7) << 16);
+
+        return(ui32IntStatus);
+    }
+    else
+    {
+        ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);
+        ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0xD) << 16);
+        return(ui32IntStatus);
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be enabled.
+//!
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DATA_OUT) ||
+           (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+    //
+    // Enable the interrupts from the flags.
+    //
+    HWREG(DTHE_BASE + DTHE_O_DES_IM)  &= ~((ui32IntFlags & 0x00070000) >> 16);
+    HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
+//!
+//! This function disables interrupt sources in the DES module.
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DATA_OUT) ||
+           (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+    //
+    // Clear the interrupts from the flags.
+    //
+    HWREG(DTHE_BASE + DTHE_O_AES_IM)  |= ((ui32IntFlags & 0x00070000) >> 16);
+    HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+}
+
+//*****************************************************************************
+//
+//! Clears interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
+//!
+//! This function disables interrupt sources in the DES module.
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt
+//!
+//! \note The DMA done interrupts are the only interrupts that can be cleared.
+//! The remaining interrupts can be disabled instead using DESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+           (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+    HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled DES interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables DES interrupts on the interrupt controller; specific DES
+//! interrupt sources must be enabled using DESIntEnable().  The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! DESIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable DES interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_DES, pfnHandler);
+
+    //
+    // Enable the interrupt.
+    //
+    IntEnable(INT_DES);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntUnregister(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(INT_DES);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_DES);
+}
+
+//*****************************************************************************
+//
+//! Enables DMA request sources in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Flags is a bit mask of the DMA requests to be enabled.
+//!
+//! This function enables DMA request sources in the DES module.  The
+//! \e ui32Flags parameter should be the logical OR of any of the following:
+//!
+//! - \b DES_DMA_CONTEXT_IN - Context In
+//! - \b DES_DMA_DATA_OUT - Data Out
+//! - \b DES_DMA_DATA_IN - Data In
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
+           (ui32Flags & DES_DMA_DATA_OUT) ||
+           (ui32Flags & DES_DMA_DATA_IN));
+
+    //
+    // Set the data in and data out DMA request enable bits.
+    //
+    HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags;
+}
+
+//*****************************************************************************
+//
+//! Disables DMA request sources in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Flags is a bit mask of the DMA requests to be disabled.
+//!
+//! This function disables DMA request sources in the DES module.  The
+//! \e ui32Flags parameter should be the logical OR of any of the following:
+//!
+//! - \b DES_DMA_CONTEXT_IN - Context In
+//! - \b DES_DMA_DATA_OUT - Data Out
+//! - \b DES_DMA_DATA_IN - Data In
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ui32Base == DES_BASE);
+    ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
+           (ui32Flags & DES_DMA_DATA_OUT) ||
+           (ui32Flags & DES_DMA_DATA_IN));
+
+    //
+    // Disable the DMA sources.
+    //
+    HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************

cc3200/hal/des.h

@@ -0,0 +1,143 @@
+//*****************************************************************************
+//
+//  des.h
+//
+//  Defines and Macros for the DES module.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_DES_H__
+#define __DRIVERLIB_DES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the direction with the
+// ui32Config argument in the DESConfig() function.  Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_DIR_DECRYPT     0x00000000
+#define DES_CFG_DIR_ENCRYPT     0x00000004
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operational with the
+// ui32Config argument in the DESConfig() function.  Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_MODE_ECB        0x00000000
+#define DES_CFG_MODE_CBC        0x00000010
+#define DES_CFG_MODE_CFB        0x00000020
+
+//*****************************************************************************
+//
+// The following defines are used to select between single DES and triple DES
+// with the ui32Config argument in the DESConfig() function.  Only one is
+// permitted.
+//
+//*****************************************************************************
+#define DES_CFG_SINGLE          0x00000000
+#define DES_CFG_TRIPLE          0x00000008
+
+//*****************************************************************************
+//
+// The following defines are used with the DESIntEnable(), DESIntDisable() and
+// DESIntStatus() functions.
+//
+//*****************************************************************************
+#define DES_INT_CONTEXT_IN      0x00000001
+#define DES_INT_DATA_IN         0x00000002
+#define DES_INT_DATA_OUT        0x00000004
+#define DES_INT_DMA_CONTEXT_IN  0x00010000
+#define DES_INT_DMA_DATA_IN     0x00020000
+#define DES_INT_DMA_DATA_OUT    0x00040000
+
+//*****************************************************************************
+//
+// The following defines are used with the DESEnableDMA() and DESDisableDMA()
+// functions.
+//
+//*****************************************************************************
+#define DES_DMA_CONTEXT_IN      0x00000080
+#define DES_DMA_DATA_OUT        0x00000040
+#define DES_DMA_DATA_IN         0x00000020
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
+                        uint8_t ui8Length);
+extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
+                                   uint8_t ui8Length);
+extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
+                           uint8_t *pui8Dest, uint32_t ui32Length);
+extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
+                         uint8_t ui8Length);
+extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
+                                    uint8_t ui8Length);
+extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
+extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void DESIntUnregister(uint32_t ui32Base);
+extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
+extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key);
+extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __DRIVERLIB_DES_H__

cc3200/hal/fault_registers.h

@@ -0,0 +1,73 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef FAULT_REGISTERS_H_
+#define FAULT_REGISTERS_H_
+
+
+typedef struct
+{
+    uint32_t    IERR        :1;
+    uint32_t    DERR        :1;
+    uint32_t                :1;
+    uint32_t    MUSTKE      :1;
+    uint32_t    MSTKE       :1;
+    uint32_t    MLSPERR     :1;
+    uint32_t                :1;
+    uint32_t    MMARV       :1;
+    uint32_t    IBUS        :1;
+    uint32_t    PRECISE     :1;
+    uint32_t    IMPRE       :1;
+    uint32_t    BUSTKE      :1;
+    uint32_t    BSTKE       :1;
+    uint32_t    BLSPERR     :1;
+    uint32_t                :1;
+    uint32_t    BFARV       :1;
+    uint32_t    UNDEF       :1;
+    uint32_t    INVSTAT     :1;
+    uint32_t    INVCP       :1;
+    uint32_t    NOCP        :1;
+    uint32_t                :4;
+    uint32_t    UNALIGN     :1;
+    uint32_t    DIVO0       :1;
+    uint32_t                :6;
+
+}_CFSR_t;
+
+
+typedef struct
+{
+
+    uint32_t    DBG         :1;
+    uint32_t    FORCED      :1;
+    uint32_t                :28;
+    uint32_t    VECT        :1;
+    uint32_t                :1;
+
+}_HFSR_t;
+
+
+#endif /* FAULT_REGISTERS_H_ */

cc3200/hal/gpio.c

@@ -0,0 +1,706 @@
+//*****************************************************************************
+//
+//  gpio.c
+//
+//  Driver for the GPIO module.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup GPIO_General_Purpose_InputOutput_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_common_reg.h"
+#include "debug.h"
+#include "gpio.h"
+#include "interrupt.h"
+
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a GPIO base address.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function determines if a GPIO port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#if defined(DEBUG) && !defined(BOOTLOADER)
+static tBoolean
+GPIOBaseValid(unsigned long ulPort)
+{
+    return((ulPort == GPIOA0_BASE) ||
+           (ulPort == GPIOA1_BASE) ||
+           (ulPort == GPIOA2_BASE) ||
+           (ulPort == GPIOA3_BASE) ||             
+           (ulPort == GPIOA4_BASE));
+}
+#else
+#define GPIOBaseValid(ulPort)         (ulPort)
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the GPIO interrupt number.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! Given a GPIO base address, returns the corresponding interrupt number.
+//!
+//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+GPIOGetIntNumber(unsigned long ulPort)
+{
+    unsigned int ulInt;
+
+    //
+    // Determine the GPIO interrupt number for the given module.
+    //
+    switch(ulPort)
+    {
+        case GPIOA0_BASE:
+        {
+            ulInt = INT_GPIOA0;
+            break;
+        }
+
+        case GPIOA1_BASE:
+        {
+            ulInt = INT_GPIOA1;
+            break;
+        }
+
+        case GPIOA2_BASE:
+        {
+            ulInt = INT_GPIOA2;
+            break;
+        }
+
+        case GPIOA3_BASE:
+        {
+            ulInt = INT_GPIOA3;
+            break;
+        }
+
+        default:
+        {
+            return(-1);
+        }
+    }
+
+    //
+    // Return GPIO interrupt number.
+    //
+    return(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Sets the direction and mode of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulPinIO is the pin direction and/or mode.
+//!
+//! This function will set the specified pin(s) on the selected GPIO port
+//! as either an input or output under software control, or it will set the
+//! pin to be under hardware control.
+//!
+//! The parameter \e ulPinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_DIR_MODE_IN
+//! - \b GPIO_DIR_MODE_OUT
+//!
+//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
+//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
+//! will be programmed as a software controlled output.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note GPIOPadConfigSet() must also be used to configure the corresponding
+//! pad(s) in order for them to propagate the signal to/from the GPIO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+               unsigned long ulPinIO)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+    ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT));
+
+    //
+    // Set the pin direction and mode.
+    //
+    HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ?
+                                  (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) :
+                                  (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the direction and mode of a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port.  The pin can be configured as either an input or
+//! output under software control, or it can be under hardware control.  The
+//! type of control and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
+{
+    unsigned long ulDir;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Return the pin direction
+    //
+    ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR);
+    return(((ulDir & ucPin) ? 1 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the interrupt type for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulIntType specifies the type of interrupt trigger mechanism.
+//!
+//! This function sets up the various interrupt trigger mechanisms for the
+//! specified pin(s) on the selected GPIO port.
+//!
+//! The parameter \e ulIntType is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_FALLING_EDGE
+//! - \b GPIO_RISING_EDGE
+//! - \b GPIO_BOTH_EDGES
+//! - \b GPIO_LOW_LEVEL
+//! - \b GPIO_HIGH_LEVEL
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note In order to avoid any spurious interrupts, the user must
+//! ensure that the GPIO inputs remain stable for the duration of
+//! this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+               unsigned long ulIntType)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+    ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
+           (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
+           (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
+
+    //
+    // Set the pin interrupt type.
+    //
+    HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ?
+                                  (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) :
+                                  (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins)));
+    HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ?
+                                 (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) :
+                                 (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins)));
+    HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ?
+                                  (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) :
+                                  (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt type for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the interrupt type for a specified pin on the selected
+//! GPIO port.  The pin can be configured as a falling edge, rising edge, or
+//! both edge detected interrupt, or it can be configured as a low level or
+//! high level detected interrupt.  The type of interrupt detection mechanism
+//! is returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIOIntTypeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
+{
+    unsigned long ulIBE, ulIS, ulIEV;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Return the pin interrupt type.
+    //
+    ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE);
+    ulIS = HWREG(ulPort + GPIO_O_GPIO_IS);
+    ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV);
+    return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
+           ((ulIEV & ucPin) ? 4 : 0));
+}
+
+//*****************************************************************************
+//
+//! Enables the specified GPIO interrupts.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to enable.
+//!
+//! This function enables the indicated GPIO interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b GPIO_INT_DMA   - interrupt due to GPIO triggered DMA Done
+//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
+//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
+//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
+//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
+//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
+//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
+//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
+//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Enable the interrupts.
+    //
+    HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the specified GPIO interrupts.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! This function disables the indicated GPIO interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b GPIO_INT_DMA   - interrupt due to GPIO triggered DMA Done
+//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
+//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
+//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
+//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
+//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
+//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
+//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
+//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Disable the interrupts.
+    //
+    HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in GPIOIntEnable().
+//
+//*****************************************************************************
+long
+GPIOIntStatus(unsigned long ulPort, tBoolean bMasked)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Return the interrupt status.
+    //
+    if(bMasked)
+    {
+        return(HWREG(ulPort + GPIO_O_GPIO_MIS));
+    }
+    else
+    {
+        return(HWREG(ulPort + GPIO_O_GPIO_RIS));
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the interrupt for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! Clears the interrupt for the specified pin(s).
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to GPIOIntEnable().
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Clear the interrupts.
+    //
+    HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! GPIO port.  This function will also enable the corresponding GPIO interrupt
+//! in the interrupt controller; individual pin interrupts and interrupt
+//! sources must be enabled with GPIOIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Get the interrupt number associated with the specified GPIO.
+    //
+    ulPort = GPIOGetIntNumber(ulPort);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ulPort, pfnIntHandler);
+
+    //
+    // Enable the GPIO interrupt.
+    //
+    IntEnable(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! GPIO port.  This function will also disable the corresponding
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
+//! and interrupt sources must be disabled with GPIOIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntUnregister(unsigned long ulPort)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Get the interrupt number associated with the specified GPIO.
+    //
+    ulPort = GPIOGetIntNumber(ulPort);
+
+    //
+    // Disable the GPIO interrupt.
+    //
+    IntDisable(ulPort);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Reads the values present of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The values at the specified pin(s) are read, as specified by \e ucPins.
+//! Values are returned for both input and output pin(s), and the value
+//! for pin(s) that are not specified by \e ucPins are set to 0.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return Returns a bit-packed byte providing the state of the specified
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
+//! GPIO port pin 1, and so on.  Any bit that is not specified by \e ucPins
+//! is returned as a 0.  Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Return the pin value(s).
+    //
+    return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ucVal is the value to write to the pin(s).
+//!
+//! Writes the corresponding bit values to the output pin(s) specified by
+//! \e ucPins.  Writing to a pin configured as an input pin has no effect.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Write the pins.
+    //
+    HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal;
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO port as a trigger to start a DMA transaction.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function enables a GPIO port to be used as a trigger to start a uDMA
+//! transaction. The GPIO pin will still generate interrupts if the interrupt is
+//! enabled for the selected pin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODMATriggerEnable(unsigned long ulPort)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Set the pin as a DMA trigger.
+    //
+    if(ulPort == GPIOA0_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1;
+    }
+    else if(ulPort == GPIOA1_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2;
+    }
+    else if(ulPort == GPIOA2_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4;
+    }
+    else if(ulPort == GPIOA3_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables a GPIO port as a trigger to start a DMA transaction.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function disables a GPIO port to be used as a trigger to start a uDMA
+//! transaction.  This function can be used to disable this feature if it was
+//! enabled via a call to GPIODMATriggerEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODMATriggerDisable(unsigned long ulPort)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Set the pin as a DMA trigger.
+    //
+    if(ulPort == GPIOA0_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1;
+    }
+    else if(ulPort == GPIOA1_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2;
+    }
+    else if(ulPort == GPIOA2_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4;
+    }
+    else if(ulPort == GPIOA3_BASE)
+    {
+      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8;
+    }
+}
+
+
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************

cc3200/hal/gpio.h

@@ -0,0 +1,139 @@
+//*****************************************************************************
+//
+//  gpio.h
+//
+//  Defines and Macros for GPIO API.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0              0x00000001  // GPIO pin 0
+#define GPIO_PIN_1              0x00000002  // GPIO pin 1
+#define GPIO_PIN_2              0x00000004  // GPIO pin 2
+#define GPIO_PIN_3              0x00000008  // GPIO pin 3
+#define GPIO_PIN_4              0x00000010  // GPIO pin 4
+#define GPIO_PIN_5              0x00000020  // GPIO pin 5
+#define GPIO_PIN_6              0x00000040  // GPIO pin 6
+#define GPIO_PIN_7              0x00000080  // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge
+#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge
+#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges
+#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level
+#define GPIO_HIGH_LEVEL         0x00000006  // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
+// in the ulIntFlags parameter.
+//
+//*****************************************************************************
+#define GPIO_INT_DMA            0x00000100
+#define GPIO_INT_PIN_0          0x00000001
+#define GPIO_INT_PIN_1          0x00000002
+#define GPIO_INT_PIN_2          0x00000004
+#define GPIO_INT_PIN_3          0x00000008
+#define GPIO_INT_PIN_4          0x00000010
+#define GPIO_INT_PIN_5          0x00000020
+#define GPIO_INT_PIN_6          0x00000040
+#define GPIO_INT_PIN_7          0x00000080
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+                           unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+                           unsigned long ulIntType);
+extern void GPIODMATriggerEnable(unsigned long ulPort);
+extern void GPIODMATriggerDisable(unsigned long ulPort);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags);
+extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags);
+extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags);
+extern void GPIOIntRegister(unsigned long ulPort,
+                                void (*pfnIntHandler)(void));
+extern void GPIOIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+                         unsigned char ucVal);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __GPIO_H__

cc3200/hal/i2c.h

@@ -0,0 +1,360 @@
+//*****************************************************************************
+//
+//  i2c.h
+//
+//  Prototypes for the I2C Driver.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_I2C_H__
+#define __DRIVERLIB_I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines for the API.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Interrupt defines.
+//
+//*****************************************************************************
+#define I2C_INT_MASTER          0x00000001
+#define I2C_INT_SLAVE           0x00000002
+
+//*****************************************************************************
+//
+// I2C Master commands.
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND                                            \
+                                0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE                                         \
+                                0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START                                       \
+                                0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT                                        \
+                                0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH                                      \
+                                0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_STOP                                        \
+                                0x00000004
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP                                  \
+                                0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START                                    \
+                                0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT                                     \
+                                0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH                                   \
+                                0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP                               \
+                                0x00000004
+#define I2C_MASTER_CMD_QUICK_COMMAND                                          \
+                                0x00000027
+#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND                                    \
+                                0x00000013
+#define I2C_MASTER_CMD_FIFO_SINGLE_SEND                                       \
+                                0x00000046
+#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE                                    \
+                                0x00000046
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_START                                  \
+                                0x00000042
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT                                   \
+                                0x00000040
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH                                 \
+                                0x00000044
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP                             \
+                                0x00000004
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START                               \
+                                0x0000004a
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT                                \
+                                0x00000048
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH                              \
+                                0x00000044
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP                          \
+                                0x00000004
+
+//*****************************************************************************
+//
+// I2C Master glitch filter configuration.
+//
+//*****************************************************************************
+#define I2C_MASTER_GLITCH_FILTER_DISABLED                                     \
+                                0
+#define I2C_MASTER_GLITCH_FILTER_1                                            \
+                                0x00010000
+#define I2C_MASTER_GLITCH_FILTER_2                                            \
+                                0x00020000
+#define I2C_MASTER_GLITCH_FILTER_3                                            \
+                                0x00030000
+#define I2C_MASTER_GLITCH_FILTER_4                                            \
+                                0x00040000
+#define I2C_MASTER_GLITCH_FILTER_8                                            \
+                                0x00050000
+#define I2C_MASTER_GLITCH_FILTER_16                                           \
+                                0x00060000
+#define I2C_MASTER_GLITCH_FILTER_32                                           \
+                                0x00070000
+
+//*****************************************************************************
+//
+// I2C Master error status.
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE     0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE      0
+#define I2C_SLAVE_ACT_RREQ      0x00000001  // Master has sent data
+#define I2C_SLAVE_ACT_TREQ      0x00000002  // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR  0x00000005  // Master has sent first byte
+#define I2C_SLAVE_ACT_OWN2SEL   0x00000008  // Master requested secondary slave
+#define I2C_SLAVE_ACT_QCMD      0x00000010  // Master has sent a Quick Command
+#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020  // Master Quick Command value
+
+//*****************************************************************************
+//
+// Miscellaneous I2C driver definitions.
+//
+//*****************************************************************************
+#define I2C_MASTER_MAX_RETRIES  1000        // Number of retries
+
+//*****************************************************************************
+//
+// I2C Master interrupts.
+//
+//*****************************************************************************
+#define I2C_MASTER_INT_RX_FIFO_FULL                                           \
+                                0x00000800  // RX FIFO Full Interrupt
+#define I2C_MASTER_INT_TX_FIFO_EMPTY                                          \
+                                0x00000400  // TX FIFO Empty Interrupt
+#define I2C_MASTER_INT_RX_FIFO_REQ                                            \
+                                0x00000200  // RX FIFO Request Interrupt
+#define I2C_MASTER_INT_TX_FIFO_REQ                                            \
+                                0x00000100  // TX FIFO Request Interrupt
+#define I2C_MASTER_INT_ARB_LOST                                               \
+                                0x00000080  // Arb Lost Interrupt
+#define I2C_MASTER_INT_STOP     0x00000040  // Stop Condition Interrupt
+#define I2C_MASTER_INT_START    0x00000020  // Start Condition Interrupt
+#define I2C_MASTER_INT_NACK     0x00000010  // Addr/Data NACK Interrupt
+#define I2C_MASTER_INT_TX_DMA_DONE                                            \
+                                0x00000008  // TX DMA Complete Interrupt
+#define I2C_MASTER_INT_RX_DMA_DONE                                            \
+                                0x00000004  // RX DMA Complete Interrupt
+#define I2C_MASTER_INT_TIMEOUT  0x00000002  // Clock Timeout Interrupt
+#define I2C_MASTER_INT_DATA     0x00000001  // Data Interrupt
+
+//*****************************************************************************
+//
+// I2C Slave interrupts.
+//
+//*****************************************************************************
+#define I2C_SLAVE_INT_RX_FIFO_FULL                                            \
+                                0x00000100  // RX FIFO Full Interrupt
+#define I2C_SLAVE_INT_TX_FIFO_EMPTY                                           \
+                                0x00000080  // TX FIFO Empty Interrupt
+#define I2C_SLAVE_INT_RX_FIFO_REQ                                             \
+                                0x00000040  // RX FIFO Request Interrupt
+#define I2C_SLAVE_INT_TX_FIFO_REQ                                             \
+                                0x00000020  // TX FIFO Request Interrupt
+#define I2C_SLAVE_INT_TX_DMA_DONE                                             \
+                                0x00000010  // TX DMA Complete Interrupt
+#define I2C_SLAVE_INT_RX_DMA_DONE                                             \
+                                0x00000008  // RX DMA Complete Interrupt
+#define I2C_SLAVE_INT_STOP      0x00000004  // Stop Condition Interrupt
+#define I2C_SLAVE_INT_START     0x00000002  // Start Condition Interrupt
+#define I2C_SLAVE_INT_DATA      0x00000001  // Data Interrupt
+
+//*****************************************************************************
+//
+// I2C Slave FIFO configuration macros.
+//
+//*****************************************************************************
+#define I2C_SLAVE_TX_FIFO_ENABLE                                              \
+                                0x00000002
+#define I2C_SLAVE_RX_FIFO_ENABLE                                              \
+                                0x00000004
+
+//*****************************************************************************
+//
+// I2C FIFO configuration macros.
+//
+//*****************************************************************************
+#define I2C_FIFO_CFG_TX_MASTER  0x00000000
+#define I2C_FIFO_CFG_TX_SLAVE   0x00008000
+#define I2C_FIFO_CFG_RX_MASTER  0x00000000
+#define I2C_FIFO_CFG_RX_SLAVE   0x80000000
+#define I2C_FIFO_CFG_TX_MASTER_DMA                                            \
+                                0x00002000
+#define I2C_FIFO_CFG_TX_SLAVE_DMA                                             \
+                                0x0000a000
+#define I2C_FIFO_CFG_RX_MASTER_DMA                                            \
+                                0x20000000
+#define I2C_FIFO_CFG_RX_SLAVE_DMA                                             \
+                                0xa0000000
+#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
+#define I2C_FIFO_CFG_TX_TRIG_1  0x00000001
+#define I2C_FIFO_CFG_TX_TRIG_2  0x00000002
+#define I2C_FIFO_CFG_TX_TRIG_3  0x00000003
+#define I2C_FIFO_CFG_TX_TRIG_4  0x00000004
+#define I2C_FIFO_CFG_TX_TRIG_5  0x00000005
+#define I2C_FIFO_CFG_TX_TRIG_6  0x00000006
+#define I2C_FIFO_CFG_TX_TRIG_7  0x00000007
+#define I2C_FIFO_CFG_TX_TRIG_8  0x00000008
+#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
+#define I2C_FIFO_CFG_RX_TRIG_1  0x00010000
+#define I2C_FIFO_CFG_RX_TRIG_2  0x00020000
+#define I2C_FIFO_CFG_RX_TRIG_3  0x00030000
+#define I2C_FIFO_CFG_RX_TRIG_4  0x00040000
+#define I2C_FIFO_CFG_RX_TRIG_5  0x00050000
+#define I2C_FIFO_CFG_RX_TRIG_6  0x00060000
+#define I2C_FIFO_CFG_RX_TRIG_7  0x00070000
+#define I2C_FIFO_CFG_RX_TRIG_8  0x00080000
+
+//*****************************************************************************
+//
+// I2C FIFO status.
+//
+//*****************************************************************************
+#define I2C_FIFO_RX_BELOW_TRIG_LEVEL                                          \
+                                0x00040000
+#define I2C_FIFO_RX_FULL        0x00020000
+#define I2C_FIFO_RX_EMPTY       0x00010000
+#define I2C_FIFO_TX_BELOW_TRIG_LEVEL                                          \
+                                0x00000004
+#define I2C_FIFO_TX_FULL        0x00000002
+#define I2C_FIFO_TX_EMPTY       0x00000001
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
+extern void I2CIntUnregister(uint32_t ui32Base);
+extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CTxFIFOFlush(uint32_t ui32Base);
+extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CRxFIFOFlush(uint32_t ui32Base);
+extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
+extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
+                                          uint8_t ui8Data);
+extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
+extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
+                                          uint8_t *pui8Data);
+extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
+                                    uint8_t ui8Length);
+extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
+extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
+                                           uint32_t ui32Config);
+extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CSlaveFIFODisable(uint32_t ui32Base);
+extern bool I2CMasterBusBusy(uint32_t ui32Base);
+extern bool I2CMasterBusy(uint32_t ui32Base);
+extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
+extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
+extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern void I2CMasterDisable(uint32_t ui32Base);
+extern void I2CMasterEnable(uint32_t ui32Base);
+extern uint32_t I2CMasterErr(uint32_t ui32Base);
+extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32SCLFreq);
+extern void I2CMasterIntClear(uint32_t ui32Base);
+extern void I2CMasterIntDisable(uint32_t ui32Base);
+extern void I2CMasterIntEnable(uint32_t ui32Base);
+extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
+extern void I2CMasterIntEnableEx(uint32_t ui32Base,
+                                 uint32_t ui32IntFlags);
+extern void I2CMasterIntDisableEx(uint32_t ui32Base,
+                                  uint32_t ui32IntFlags);
+extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
+                                       bool bMasked);
+extern void I2CMasterIntClearEx(uint32_t ui32Base,
+                                uint32_t ui32IntFlags);
+extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
+extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
+extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
+extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
+extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
+                                  uint8_t ui8SlaveAddr,
+                                  bool bReceive);
+extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
+extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern void I2CSlaveDisable(uint32_t ui32Base);
+extern void I2CSlaveEnable(uint32_t ui32Base);
+extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
+extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
+                                 uint8_t ui8SlaveAddr);
+extern void I2CSlaveIntClear(uint32_t ui32Base);
+extern void I2CSlaveIntDisable(uint32_t ui32Base);
+extern void I2CSlaveIntEnable(uint32_t ui32Base);
+extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
+                                 uint32_t ui32IntFlags);
+extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
+extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
+                                      bool bMasked);
+extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_I2C_H__

cc3200/hal/i2s.h

@@ -0,0 +1,218 @@
+//*****************************************************************************
+//
+//  i2s.h
+//
+//  Defines and Macros for the I2S.
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// I2S DMA ports.
+//
+//*****************************************************************************
+#define I2S_TX_DMA_PORT      0x4401E200
+#define I2S_RX_DMA_PORT      0x4401E280
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.
+//
+//*****************************************************************************
+#define I2S_SLOT_SIZE_8       0x00300032
+#define I2S_SLOT_SIZE_16      0x00700074
+#define I2S_SLOT_SIZE_24      0x00B000B6
+
+
+#define I2S_PORT_CPU          0x00080008
+#define I2S_PORT_DMA          0x00000000
+
+#define I2S_MODE_MASTER       0x00000000
+#define I2S_MODE_SLAVE        0x00008000
+
+//*****************************************************************************
+//
+// Values that can be passed as ulDataLine parameter.
+//
+//*****************************************************************************
+#define I2S_DATA_LINE_0       0x00000001
+#define I2S_DATA_LINE_1       0x00000002
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SSerializerConfig() as the ulSerMode
+// parameter.
+//
+//*****************************************************************************
+#define I2S_SER_MODE_TX       0x00000001
+#define I2S_SER_MODE_RX       0x00000002
+#define I2S_SER_MODE_DISABLE  0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SSerializerConfig() as the ulInActState
+// parameter.
+//
+//*****************************************************************************
+#define I2S_INACT_TRI_STATE   0x00000000
+#define I2S_INACT_LOW_LEVEL   0x00000008
+#define I2S_INACT_HIGH_LEVEL  0x0000000C
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the
+// ulIntFlags parameter.
+//
+//*****************************************************************************
+#define I2S_INT_XUNDRN	      0x00000001
+#define I2S_INT_XSYNCERR      0x00000002
+#define I2S_INT_XLAST         0x00000010
+#define I2S_INT_XDATA         0x00000020
+#define I2S_INT_XSTAFRM       0x00000080
+#define I2S_INT_XDMA	      0x80000000
+#define I2S_INT_ROVRN         0x00010000
+#define I2S_INT_RSYNCERR      0x00020000
+#define I2S_INT_RLAST         0x00100000
+#define I2S_INT_RDATA         0x00200000
+#define I2S_INT_RSTAFRM       0x00800000
+#define I2S_INT_RDMA          0x40000000
+
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet
+//
+//*****************************************************************************
+#define I2S_ACT_SLOT_EVEN     0x00000001
+#define I2S_ACT_SLOT_ODD      0x00000002
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SIntClear() as the
+// ulIntFlags parameter and returned from I2SIntStatus().
+//
+//*****************************************************************************
+#define I2S_STS_XERR          0x00000100
+#define I2S_STS_XDMAERR	      0x00000080
+#define I2S_STS_XSTAFRM	      0x00000040
+#define I2S_STS_XDATA	      0x00000020
+#define I2S_STS_XLAST	      0x00000010
+#define I2S_STS_XSYNCERR      0x00000002
+#define I2S_STS_XUNDRN	      0x00000001
+#define I2S_STS_XDMA	      0x80000000
+#define I2S_STS_RERR          0x01000000
+#define I2S_STS_RDMAERR       0x00800000
+#define I2S_STS_RSTAFRM       0x00400000
+#define I2S_STS_RDATA         0x00200000
+#define I2S_STS_RLAST         0x00100000
+#define I2S_STS_RSYNCERR      0x00020000
+#define I2S_STS_ROVERN	      0x00010000
+#define I2S_STS_RDMA          0x40000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SEnable() as the ulMode parameter.
+//
+//*****************************************************************************
+#define I2S_MODE_TX_ONLY      0x00000001
+#define I2S_MODE_TX_RX_SYNC   0x00000003
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void I2SEnable(unsigned long ulBase, unsigned long ulMode);
+extern void I2SDisable(unsigned long ulBase);
+
+extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,
+                unsigned long ulData);
+extern long I2SDataPutNonBlocking(unsigned long ulBase,
+                               unsigned long ulDataLine, unsigned long ulData);
+
+extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,
+                unsigned long *pulData);
+extern long I2SDataGetNonBlocking(unsigned long ulBase,
+                unsigned long ulDataLine, unsigned long *pulData);
+
+extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
+                               unsigned long ulBitClk, unsigned long ulConfig);
+
+extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,
+                     unsigned long ulWordsPerTransfer);
+extern void I2STxFIFODisable(unsigned long ulBase);
+extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,
+                     unsigned long ulWordsPerTransfer);
+extern void I2SRxFIFODisable(unsigned long ulBase);
+extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase);
+extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase);
+
+extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,
+                         unsigned long ulSerMode, unsigned long ulInActState);
+
+extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long I2SIntStatus(unsigned long ulBase);
+extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void I2SIntUnregister(unsigned long ulBase);
+extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
+extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__I2S_H__
+

cc3200/hal/inc/asmdefs.h

@@ -0,0 +1,229 @@
+//*****************************************************************************
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__             module
+#define __TEXT__                rseg CODE:CODE(2)
+#define __DATA__                rseg DATA:DATA(2)
+#define __BSS__                 rseg DATA:DATA(2)
+#define __TEXT_NOROOT__         rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               alignrom 2
+#define __END__                 end
+#define __EXPORT__              export
+#define __IMPORT__              import
+#define __LABEL__
+#define __STR__                 dcb
+#define __THUMB_LABEL__         thumb
+#define __WORD__                dcd
+#define __INLINE_DATA__         data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    thumb
+    require8
+    preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__             ;
+#define __TEXT__                area ||.text||, code, readonly, align=2
+#define __DATA__                area ||.data||, data, align=2
+#define __BSS__                 area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__         area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               align 4
+#define __END__                 end
+#define __EXPORT__              export
+#define __IMPORT__              import
+#define __LABEL__
+#define __STR__                 dcb
+#define __THUMB_LABEL__
+#define __WORD__                dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+    .syntax unified
+    .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__             @
+#define __TEXT__                .text
+#define __DATA__                .data
+#define __BSS__                 .bss
+#define __TEXT_NOROOT__         .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__               .balign 4
+#define __END__                 .end
+#define __EXPORT__              .globl
+#define __IMPORT__              .extern
+#define __LABEL__               :
+#define __STR__                 .ascii
+#define __THUMB_LABEL__         .thumb_func
+#define __WORD__                .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__

cc3200/hal/inc/hw_adc.h

@@ -0,0 +1,888 @@
+//*****************************************************************************
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ADC_CTRL          0x00000000  // ADC control register.
+#define ADC_O_adc_ch0_gain      0x00000004  // Channel 0 gain setting
+#define ADC_O_adc_ch1_gain      0x00000008  // Channel 1 gain setting
+#define ADC_O_adc_ch2_gain      0x0000000C  // Channel 2 gain setting
+#define ADC_O_adc_ch3_gain      0x00000010  // Channel 3 gain setting
+#define ADC_O_adc_ch4_gain      0x00000014  // Channel 4 gain setting
+#define ADC_O_adc_ch5_gain      0x00000018  // Channel 5 gain setting
+#define ADC_O_adc_ch6_gain      0x0000001C  // Channel 6 gain setting
+#define ADC_O_adc_ch7_gain      0x00000020  // Channel 7 gain setting
+#define ADC_O_adc_ch0_irq_en    0x00000024  // Channel 0 interrupt enable
+                                            // register
+#define ADC_O_adc_ch1_irq_en    0x00000028  // Channel 1 interrupt enable
+                                            // register
+#define ADC_O_adc_ch2_irq_en    0x0000002C  // Channel 2 interrupt enable
+                                            // register
+#define ADC_O_adc_ch3_irq_en    0x00000030  // Channel 3 interrupt enable
+                                            // register
+#define ADC_O_adc_ch4_irq_en    0x00000034  // Channel 4 interrupt enable
+                                            // register
+#define ADC_O_adc_ch5_irq_en    0x00000038  // Channel 5 interrupt enable
+                                            // register
+#define ADC_O_adc_ch6_irq_en    0x0000003C  // Channel 6 interrupt enable
+                                            // register
+#define ADC_O_adc_ch7_irq_en    0x00000040  // Channel 7 interrupt enable
+                                            // register
+#define ADC_O_adc_ch0_irq_status \
+                                0x00000044  // Channel 0 interrupt status
+                                            // register
+
+#define ADC_O_adc_ch1_irq_status \
+                                0x00000048  // Channel 1 interrupt status
+                                            // register
+
+#define ADC_O_adc_ch2_irq_status \
+                                0x0000004C
+
+#define ADC_O_adc_ch3_irq_status \
+                                0x00000050  // Channel 3 interrupt status
+                                            // register
+
+#define ADC_O_adc_ch4_irq_status \
+                                0x00000054  // Channel 4 interrupt status
+                                            // register
+
+#define ADC_O_adc_ch5_irq_status \
+                                0x00000058
+
+#define ADC_O_adc_ch6_irq_status \
+                                0x0000005C  // Channel 6 interrupt status
+                                            // register
+
+#define ADC_O_adc_ch7_irq_status \
+                                0x00000060  // Channel 7 interrupt status
+                                            // register
+
+#define ADC_O_adc_dma_mode_en   0x00000064  // DMA mode enable register
+#define ADC_O_adc_timer_configuration \
+                                0x00000068  // ADC timer configuration register
+
+#define ADC_O_adc_timer_current_count \
+                                0x00000070  // ADC timer current count register
+
+#define ADC_O_channel0FIFODATA  0x00000074  // CH0 FIFO DATA register
+#define ADC_O_channel1FIFODATA  0x00000078  // CH1 FIFO DATA register
+#define ADC_O_channel2FIFODATA  0x0000007C  // CH2 FIFO DATA register
+#define ADC_O_channel3FIFODATA  0x00000080  // CH3 FIFO DATA register
+#define ADC_O_channel4FIFODATA  0x00000084  // CH4 FIFO DATA register
+#define ADC_O_channel5FIFODATA  0x00000088  // CH5 FIFO DATA register
+#define ADC_O_channel6FIFODATA  0x0000008C  // CH6 FIFO DATA register
+#define ADC_O_channel7FIFODATA  0x00000090  // CH7 FIFO DATA register
+#define ADC_O_adc_ch0_fifo_lvl  0x00000094  // channel 0 FIFO Level register
+#define ADC_O_adc_ch1_fifo_lvl  0x00000098  // Channel 1 interrupt status
+                                            // register
+#define ADC_O_adc_ch2_fifo_lvl  0x0000009C
+#define ADC_O_adc_ch3_fifo_lvl  0x000000A0  // Channel 3 interrupt status
+                                            // register
+#define ADC_O_adc_ch4_fifo_lvl  0x000000A4  // Channel 4 interrupt status
+                                            // register
+#define ADC_O_adc_ch5_fifo_lvl  0x000000A8
+#define ADC_O_adc_ch6_fifo_lvl  0x000000AC  // Channel 6 interrupt status
+                                            // register
+#define ADC_O_adc_ch7_fifo_lvl  0x000000B0  // Channel 7 interrupt status
+                                            // register
+
+#define ADC_O_ADC_CH_ENABLE     0x000000B8
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ADC_CTRL register.
+//
+//******************************************************************************
+#define ADC_ADC_CTRL_adc_cap_scale \
+                                0x00000020  // ADC CAP SCALE.
+
+#define ADC_ADC_CTRL_adc_buf_bypass \
+                                0x00000010  // ADC ANA CIO buffer bypass.
+                                            // Signal is modelled in ANA TOP.
+                                            // When '1': ADC buffer is bypassed.
+
+#define ADC_ADC_CTRL_adc_buf_en 0x00000008  // ADC ANA buffer enable. When 1:
+                                            // ADC buffer is enabled.
+#define ADC_ADC_CTRL_adc_core_en \
+                                0x00000004  // ANA ADC core en. This signal act
+                                            // as glbal enable to ADC CIO. When
+                                            // 1: ADC core is enabled.
+
+#define ADC_ADC_CTRL_adc_soft_reset \
+                                0x00000002  // ADC soft reset. When '1' : reset
+                                            // ADC internal logic.
+
+#define ADC_ADC_CTRL_adc_en     0x00000001  // ADC global enable. When set ADC
+                                            // module is enabled
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_gain_adc_channel0_gain_M \
+                                0x00000003  // gain setting for ADC channel 0.
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch0_gain_adc_channel0_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_gain_adc_channel1_gain_M \
+                                0x00000003  // gain setting for ADC channel 1.
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch1_gain_adc_channel1_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_gain_adc_channel2_gain_M \
+                                0x00000003  // gain setting for ADC channel 2.
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch2_gain_adc_channel2_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_gain_adc_channel3_gain_M \
+                                0x00000003  // gain setting for ADC channel 3.
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch3_gain_adc_channel3_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_gain_adc_channel4_gain_M \
+                                0x00000003  // gain setting for ADC channel 4
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch4_gain_adc_channel4_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_gain_adc_channel5_gain_M \
+                                0x00000003  // gain setting for ADC channel 5.
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch5_gain_adc_channel5_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_gain_adc_channel6_gain_M \
+                                0x00000003  // gain setting for ADC channel 6
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch6_gain_adc_channel6_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_gain_adc_channel7_gain_M \
+                                0x00000003  // gain setting for ADC channel 7.
+                                            // when "00": 1x when "01: 2x when
+                                            // "10":3x when "11" 4x
+
+#define ADC_adc_ch7_gain_adc_channel7_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \
+                                0x0000000F  // interrupt enable register for
+                                            // per ADC channel bit 3: when '1'
+                                            // -> enable FIFO overflow interrupt
+                                            // bit 2: when '1' -> enable FIFO
+                                            // underflow interrupt bit 1: when
+                                            // "1' -> enable FIFO empty
+                                            // interrupt bit 0: when "1" ->
+                                            // enable FIFO full interrupt
+
+#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \
+                                0x0000000F  // interrupt status register for
+                                            // per ADC channel. Interrupt status
+                                            // can be cleared on write. bit 3:
+                                            // when value '1' is written ->
+                                            // would clear FIFO overflow
+                                            // interrupt status in the next
+                                            // cycle. if same interrupt is set
+                                            // in the same cycle then interurpt
+                                            // would be set and clear command
+                                            // will be ignored. bit 2: when
+                                            // value '1' is written -> would
+                                            // clear FIFO underflow interrupt
+                                            // status in the next cycle. bit 1:
+                                            // when value '1' is written ->
+                                            // would clear FIFO empty interrupt
+                                            // status in the next cycle. bit 0:
+                                            // when value '1' is written ->
+                                            // would clear FIFO full interrupt
+                                            // status in the next cycle.
+
+#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_dma_mode_en register.
+//
+//******************************************************************************
+#define ADC_adc_dma_mode_en_DMA_MODEenable_M \
+                                0x000000FF  // this register enable DMA mode.
+                                            // when '1' respective ADC channel
+                                            // is enabled for DMA. When '0' only
+                                            // interrupt mode is enabled. Bit 0:
+                                            // channel 0 DMA mode enable. Bit 1:
+                                            // channel 1 DMA mode enable. Bit 2:
+                                            // channel 2 DMA mode enable. Bit 3:
+                                            // channel 3 DMA mode enable. bit 4:
+                                            // channel 4 DMA mode enable. bit 5:
+                                            // channel 5 DMA mode enable. bit 6:
+                                            // channel 6 DMA mode enable. bit 7:
+                                            // channel 7 DMA mode enable.
+
+#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_timer_configuration register.
+//
+//******************************************************************************
+#define ADC_adc_timer_configuration_timeren \
+                                0x02000000  // when '1' timer is enabled.
+
+#define ADC_adc_timer_configuration_timerreset \
+                                0x01000000  // when '1' reset timer.
+
+#define ADC_adc_timer_configuration_timercount_M \
+                                0x00FFFFFF  // Timer count configuration. 17
+                                            // bit counter is supported. Other
+                                            // MSB's are redundent.
+
+#define ADC_adc_timer_configuration_timercount_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_timer_current_count register.
+//
+//******************************************************************************
+#define ADC_adc_timer_current_count_timercurrentcount_M \
+                                0x0001FFFF  // Timer count configuration
+
+#define ADC_adc_timer_current_count_timercurrentcount_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel0FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel1FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel2FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel3FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel4FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel5FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel6FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel7FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \
+                                0xFFFFFFFF  // read to this register would
+                                            // return ADC data along with time
+                                            // stamp information in following
+                                            // format: bits [13:0] : ADC sample
+                                            // bits [31:14]: : time stamp per
+                                            // ADC sample
+
+#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \
+                                0x00000007  // This register shows current FIFO
+                                            // level. FIFO is 4 word wide.
+                                            // Possible supported levels are :
+                                            // 0x0 to 0x3
+
+#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0
+
+
+
+#endif // __HW_ADC_H__

cc3200/hal/inc/hw_aes.h

@@ -0,0 +1,802 @@
+//*****************************************************************************
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_AES_H__
+#define __HW_AES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the AES_P register offsets.
+//
+//*****************************************************************************
+#define AES_O_KEY2_6          0x00000000  // XTS second key / CBC-MAC third
+                                            // key
+#define AES_O_KEY2_7          0x00000004  // XTS second key (MSW for 256-bit
+                                            // key) / CBC-MAC third key (MSW)
+#define AES_O_KEY2_4          0x00000008  // XTS / CCM second key / CBC-MAC
+                                            // third key (LSW)
+#define AES_O_KEY2_5          0x0000000C  // XTS second key (MSW for 192-bit
+                                            // key) / CBC-MAC third key
+#define AES_O_KEY2_2          0x00000010  // XTS / CCM / CBC-MAC second key /
+                                            // Hash Key input
+#define AES_O_KEY2_3          0x00000014  // XTS second key (MSW for 128-bit
+                                            // key) + CCM/CBC-MAC second key
+                                            // (MSW) / Hash Key input (MSW)
+#define AES_O_KEY2_0          0x00000018  // XTS / CCM / CBC-MAC second key
+                                            // (LSW) / Hash Key input (LSW)
+#define AES_O_KEY2_1          0x0000001C  // XTS / CCM / CBC-MAC second key /
+                                            // Hash Key input
+#define AES_O_KEY1_6          0x00000020  // Key (LSW for 256-bit key)
+#define AES_O_KEY1_7          0x00000024  // Key (MSW for 256-bit key)
+#define AES_O_KEY1_4          0x00000028  // Key (LSW for 192-bit key)
+#define AES_O_KEY1_5          0x0000002C  // Key (MSW for 192-bit key)
+#define AES_O_KEY1_2          0x00000030  // Key
+#define AES_O_KEY1_3          0x00000034  // Key (MSW for 128-bit key)
+#define AES_O_KEY1_0          0x00000038  // Key (LSW for 128-bit key)
+#define AES_O_KEY1_1          0x0000003C  // Key
+#define AES_O_IV_IN_0         0x00000040  // Initialization Vector input
+                                            // (LSW)
+#define AES_O_IV_IN_1         0x00000044  // Initialization vector input
+#define AES_O_IV_IN_2         0x00000048  // Initialization vector input
+#define AES_O_IV_IN_3         0x0000004C  // Initialization Vector input
+                                            // (MSW)
+#define AES_O_CTRL            0x00000050  // register determines the mode of
+                                            // operation of the AES Engine
+#define AES_O_C_LENGTH_0      0x00000054  // Crypto data length registers
+                                            // (LSW and MSW) store the
+                                            // cryptographic data length in
+                                            // bytes for all modes. Once
+                                            // processing with this context is
+                                            // started@@ this length decrements
+                                            // to zero. Data lengths up to (2^61
+                                            // – 1) bytes are allowed. For GCM@@
+                                            // any value up to 2^36 - 32 bytes
+                                            // can be used. This is because a
+                                            // 32-bit counter mode is used; the
+                                            // maximum number of 128-bit blocks
+                                            // is 2^32 – 2@@ resulting in a
+                                            // maximum number of bytes of 2^36 -
+                                            // 32. A write to this register
+                                            // triggers the engine to start
+                                            // using this context. This is valid
+                                            // for all modes except GCM and CCM.
+                                            // Note that for the combined
+                                            // modes@@ this length does not
+                                            // include the authentication only
+                                            // data; the authentication length
+                                            // is specified in the
+                                            // AES_AUTH_LENGTH register below.
+                                            // All modes must have a length > 0.
+                                            // For the combined modes@@ it is
+                                            // allowed to have one of the
+                                            // lengths equal to zero. For the
+                                            // basic encryption modes
+                                            // (ECB/CBC/CTR/ICM/CFB128) it is
+                                            // allowed to program zero to the
+                                            // length field; in that case the
+                                            // length is assumed infinite. All
+                                            // data must be byte (8-bit)
+                                            // aligned; bit aligned data streams
+                                            // are not supported by the AES
+                                            // Engine. For a Host read
+                                            // operation@@ these registers
+                                            // return all-zeroes.
+#define AES_O_C_LENGTH_1      0x00000058  // Crypto data length registers
+                                            // (LSW and MSW) store the
+                                            // cryptographic data length in
+                                            // bytes for all modes. Once
+                                            // processing with this context is
+                                            // started@@ this length decrements
+                                            // to zero. Data lengths up to (2^61
+                                            // – 1) bytes are allowed. For GCM@@
+                                            // any value up to 2^36 - 32 bytes
+                                            // can be used. This is because a
+                                            // 32-bit counter mode is used; the
+                                            // maximum number of 128-bit blocks
+                                            // is 2^32 – 2@@ resulting in a
+                                            // maximum number of bytes of 2^36 -
+                                            // 32. A write to this register
+                                            // triggers the engine to start
+                                            // using this context. This is valid
+                                            // for all modes except GCM and CCM.
+                                            // Note that for the combined
+                                            // modes@@ this length does not
+                                            // include the authentication only
+                                            // data; the authentication length
+                                            // is specified in the
+                                            // AES_AUTH_LENGTH register below.
+                                            // All modes must have a length > 0.
+                                            // For the combined modes@@ it is
+                                            // allowed to have one of the
+                                            // lengths equal to zero. For the
+                                            // basic encryption modes
+                                            // (ECB/CBC/CTR/ICM/CFB128) it is
+                                            // allowed to program zero to the
+                                            // length field; in that case the
+                                            // length is assumed infinite. All
+                                            // data must be byte (8-bit)
+                                            // aligned; bit aligned data streams
+                                            // are not supported by the AES
+                                            // Engine. For a Host read
+                                            // operation@@ these registers
+                                            // return all-zeroes.
+#define AES_O_AUTH_LENGTH     0x0000005C  // AAD data length. The
+                                            // authentication length register
+                                            // store the authentication data
+                                            // length in bytes for combined
+                                            // modes only (GCM or CCM) Supported
+                                            // AAD-lengths for CCM are from 0 to
+                                            // (2^16 - 2^8) bytes. For GCM any
+                                            // value up to (2^32 - 1) bytes can
+                                            // be used. Once processing with
+                                            // this context is started@@ this
+                                            // length decrements to zero. A
+                                            // write to this register triggers
+                                            // the engine to start using this
+                                            // context for GCM and CCM. For XTS
+                                            // this register is optionally used
+                                            // to load ‘j’. Loading of ‘j’ is
+                                            // only required if ‘j’ != 0. ‘j’ is
+                                            // a 28-bit value and must be
+                                            // written to bits [31-4] of this
+                                            // register. ‘j’ represents the
+                                            // sequential number of the 128-bit
+                                            // block inside the data unit. For
+                                            // the first block in a unit@@ this
+                                            // value is zero. It is not required
+                                            // to provide a ‘j’ for each new
+                                            // data block within a unit. Note
+                                            // that it is possible to start with
+                                            // a ‘j’ unequal to zero; refer to
+                                            // Table 4 for more details. For a
+                                            // Host read operation@@ these
+                                            // registers return all-zeroes.
+#define AES_O_DATA_IN_0       0x00000060  // Data register to read and write
+                                            // plaintext/ciphertext (MSW)
+#define AES_O_DATA_IN_1       0x00000064  // Data register to read and write
+                                            // plaintext/ciphertext
+#define AES_O_DATA_IN_2       0x00000068  // Data register to read and write
+                                            // plaintext/ciphertext
+#define AES_O_DATA_IN_3       0x0000006C  // Data register to read and write
+                                            // plaintext/ciphertext (LSW)
+#define AES_O_TAG_OUT_0       0x00000070
+#define AES_O_TAG_OUT_1       0x00000074
+#define AES_O_TAG_OUT_2       0x00000078
+#define AES_O_TAG_OUT_3       0x0000007C
+#define AES_O_REVISION        0x00000080  // Register AES_REVISION
+#define AES_O_SYSCONFIG       0x00000084  // Register AES_SYSCONFIG.This
+                                            // register configures the DMA
+                                            // signals and controls the IDLE and
+                                            // reset logic
+#define AES_O_SYSSTATUS       0x00000088
+#define AES_O_IRQSTATUS       0x0000008C  // This register indicates the
+                                            // interrupt status. If one of the
+                                            // interrupt bits is set the
+                                            // interrupt output will be asserted
+#define AES_O_IRQENABLE       0x00000090  // This register contains an enable
+                                            // bit for each unique interrupt
+                                            // generated by the module. It
+                                            // matches the layout of
+                                            // AES_IRQSTATUS register. An
+                                            // interrupt is enabled when the bit
+                                            // in this register is set to ‘1’.
+                                            // An interrupt that is enabled is
+                                            // propagated to the SINTREQUEST_x
+                                            // output. All interrupts need to be
+                                            // enabled explicitly by writing
+                                            // this register.
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_6 register.
+//
+//******************************************************************************
+#define AES_KEY2_6_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_6_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_7 register.
+//
+//******************************************************************************
+#define AES_KEY2_7_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_7_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_4 register.
+//
+//******************************************************************************
+#define AES_KEY2_4_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_4_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_5 register.
+//
+//******************************************************************************
+#define AES_KEY2_5_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_5_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_2 register.
+//
+//******************************************************************************
+#define AES_KEY2_2_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_2_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_3 register.
+//
+//******************************************************************************
+#define AES_KEY2_3_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_3_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_0 register.
+//
+//******************************************************************************
+#define AES_KEY2_0_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_0_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_1 register.
+//
+//******************************************************************************
+#define AES_KEY2_1_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY2_1_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_6 register.
+//
+//******************************************************************************
+#define AES_KEY1_6_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_6_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_7 register.
+//
+//******************************************************************************
+#define AES_KEY1_7_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_7_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_4 register.
+//
+//******************************************************************************
+#define AES_KEY1_4_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_4_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_5 register.
+//
+//******************************************************************************
+#define AES_KEY1_5_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_5_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_2 register.
+//
+//******************************************************************************
+#define AES_KEY1_2_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_2_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_3 register.
+//
+//******************************************************************************
+#define AES_KEY1_3_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_3_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_0 register.
+//
+//******************************************************************************
+#define AES_KEY1_0_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_0_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_1 register.
+//
+//******************************************************************************
+#define AES_KEY1_1_KEY_M      0xFFFFFFFF  // key data
+#define AES_KEY1_1_KEY_S      0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
+//
+//******************************************************************************
+#define AES_IV_IN_0_DATA_M    0xFFFFFFFF  // IV data
+#define AES_IV_IN_0_DATA_S    0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
+//
+//******************************************************************************
+#define AES_IV_IN_1_DATA_M    0xFFFFFFFF  // IV data
+#define AES_IV_IN_1_DATA_S    0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
+//
+//******************************************************************************
+#define AES_IV_IN_2_DATA_M    0xFFFFFFFF  // IV data
+#define AES_IV_IN_2_DATA_S    0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
+//
+//******************************************************************************
+#define AES_IV_IN_3_DATA_M    0xFFFFFFFF  // IV data
+#define AES_IV_IN_3_DATA_S    0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_CTRL register.
+//
+//******************************************************************************
+#define AES_CTRL_CONTEXT_READY \
+                                0x80000000  // If ‘1’@@ this read-only status
+                                            // bit indicates that the context
+                                            // data registers can be overwritten
+                                            // and the host is permitted to
+                                            // write the next context.
+
+#define AES_CTRL_SVCTXTRDY \
+                                0x40000000  // If ‘1’@@ this read-only status
+                                            // bit indicates that an AES
+                                            // authentication TAG and/or IV
+                                            // block(s) is/are available for the
+                                            // host to retrieve. This bit is
+                                            // only asserted if the
+                                            // ‘save_context’ bit is set to ‘1’.
+                                            // The bit is mutual exclusive with
+                                            // the ‘context_ready’ bit.
+
+#define AES_CTRL_SAVE_CONTEXT 0x20000000  // This bit is used to indicate
+                                            // that an authentication TAG or
+                                            // result IV needs to be stored as a
+                                            // result context. If this bit is
+                                            // set@@ context output DMA and/or
+                                            // interrupt will be asserted if the
+                                            // operation is finished and related
+                                            // signals are enabled.
+#define AES_CTRL_CCM_M      0x01C00000  // Defines “M” that indicated the
+                                            // length of the authentication
+                                            // field for CCM operations; the
+                                            // authentication field length
+                                            // equals two times (the value of
+                                            // CCM-M plus one). Note that the
+                                            // AES Engine always returns a
+                                            // 128-bit authentication field@@ of
+                                            // which the M least significant
+                                            // bytes are valid. All values are
+                                            // supported.
+#define AES_CTRL_CCM_S      22
+#define AES_CTRL_CCM_L_M      0x00380000  // Defines “L” that indicated the
+                                            // width of the length field for CCM
+                                            // operations; the length field in
+                                            // bytes equals the value of CMM-L
+                                            // plus one. Supported values for L
+                                            // are (programmed value): 2 (1)@@ 4
+                                            // (3) and 8 (7).
+#define AES_CTRL_CCM_L_S      19
+#define AES_CTRL_CCM          0x00040000  // AES-CCM is selected@@ this is a
+                                            // combined mode@@ using AES for
+                                            // both authentication and
+                                            // encryption. No additional mode
+                                            // selection is required. 0 Other
+                                            // mode selected 1 ccm mode selected
+#define AES_CTRL_GCM_M        0x00030000  // AES-GCM mode is selected.this is
+                                            // a combined mode@@ using the
+                                            // Galois field multiplier GF(2^128)
+                                            // for authentication and AES-CTR
+                                            // mode for encryption@@ the bits
+                                            // specify the GCM mode. 0x0 No
+                                            // operation 0x1 GHASH with H loaded
+                                            // and Y0-encrypted forced to zero
+                                            // 0x2 GHASH with H loaded and
+                                            // Y0-encrypted calculated
+                                            // internally 0x3 Autonomous GHASH
+                                            // (both H and Y0-encrypted
+                                            // calculated internally)
+#define AES_CTRL_GCM_S        16
+#define AES_CTRL_CBCMAC       0x00008000  // AES-CBC MAC is selected@@ the
+                                            // Direction bit must be set to ‘1’
+                                            // for this mode. 0 Other mode
+                                            // selected 1 cbcmac mode selected
+#define AES_CTRL_F9           0x00004000  // AES f9 mode is selected@@ the
+                                            // AES key size must be set to
+                                            // 128-bit for this mode. 0 Other
+                                            // mode selected 1 f9 selected
+#define AES_CTRL_F8           0x00002000  // AES f8 mode is selected@@ the
+                                            // AES key size must be set to
+                                            // 128-bit for this mode. 0 Other
+                                            // mode selected 1 f8 selected
+#define AES_CTRL_XTS_M        0x00001800  // AES-XTS operation is selected;
+                                            // the bits specify the XTS mode.01
+                                            // = Previous/intermediate tweak
+                                            // value and ‘j’ loaded (value is
+                                            // loaded via IV@@ j is loaded via
+                                            // the AAD length register) 0x0 No
+                                            // operation 0x1
+                                            // Previous/intermediate tweak value
+                                            // and ‘j’ loaded (value is loaded
+                                            // via IV@@ j is loaded via the AAD
+                                            // length register) 0x2 Key2@@ i and
+                                            // j loaded (i is loaded via IV@@ j
+                                            // is loaded via the AAD length
+                                            // register) 0x3 Key2 and i loaded@@
+                                            // j=0 (i is loaded via IV)
+#define AES_CTRL_XTS_S        11
+#define AES_CTRL_CFB          0x00000400  // full block AES cipher feedback
+                                            // mode (CFB128) is selected. 0
+                                            // other mode selected 1 cfb
+                                            // selected
+#define AES_CTRL_ICM          0x00000200  // AES integer counter mode (ICM)
+                                            // is selected@@ this is a counter
+                                            // mode with a 16-bit wide counter.
+                                            // 0 Other mode selected. 1 ICM mode
+                                            // selected
+#define AES_CTRL_CTR_WIDTH_M  0x00000180  // Specifies the counter width for
+                                            // AES-CTR mode 0x0 Counter is 32
+                                            // bits 0x1 Counter is 64 bits 0x2
+                                            // Counter is 128 bits 0x3 Counter
+                                            // is 192 bits
+#define AES_CTRL_CTR_WIDTH_S  7
+#define AES_CTRL_CTR          0x00000040  // Tthis bit must also be set for
+                                            // GCM and CCM@@ when
+                                            // encryption/decryption is
+                                            // required. 0 Other mode selected 1
+                                            // Counter mode
+#define AES_CTRL_MODE         0x00000020  // ecb/cbc mode 0 ecb mode 1 cbc
+                                            // mode
+#define AES_CTRL_KEY_SIZE_M   0x00000018  // key size 0x0 reserved 0x1 Key is
+                                            // 128 bits. 0x2 Key is 192 bits 0x3
+                                            // Key is 256
+#define AES_CTRL_KEY_SIZE_S   3
+#define AES_CTRL_DIRECTION    0x00000004  // If set to ‘1’ an encrypt
+                                            // operation is performed. If set to
+                                            // ‘0’ a decrypt operation is
+                                            // performed. Read 0 decryption is
+                                            // selected Read 1 Encryption is
+                                            // selected
+#define AES_CTRL_INPUT_READY  0x00000002  // If ‘1’@@ this read-only status
+                                            // bit indicates that the 16-byte
+                                            // input buffer is empty@@ and the
+                                            // host is permitted to write the
+                                            // next block of data.
+#define AES_CTRL_OUTPUT_READY 0x00000001  // If ‘1’@@ this read-only status
+                                            // bit indicates that an AES output
+                                            // block is available for the host
+                                            // to retrieve.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// AES_O_C_LENGTH_0 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// AES_O_C_LENGTH_1 register.
+//
+//******************************************************************************
+#define AES_C_LENGTH_1_LENGTH_M \
+                                0x1FFFFFFF  // Data length (MSW) length
+                                            // registers (LSW and MSW) store the
+                                            // cryptographic data length in
+                                            // bytes for all modes. Once
+                                            // processing with this context is
+                                            // started@@ this length decrements
+                                            // to zero. Data lengths up to (2^61
+                                            // – 1) bytes are allowed. For GCM@@
+                                            // any value up to 2^36 - 32 bytes
+                                            // can be used. This is because a
+                                            // 32-bit counter mode is used; the
+                                            // maximum number of 128-bit blocks
+                                            // is 2^32 – 2@@ resulting in a
+                                            // maximum number of bytes of 2^36 -
+                                            // 32. A write to this register
+                                            // triggers the engine to start
+                                            // using this context. This is valid
+                                            // for all modes except GCM and CCM.
+                                            // Note that for the combined
+                                            // modes@@ this length does not
+                                            // include the authentication only
+                                            // data; the authentication length
+                                            // is specified in the
+                                            // AES_AUTH_LENGTH register below.
+                                            // All modes must have a length > 0.
+                                            // For the combined modes@@ it is
+                                            // allowed to have one of the
+                                            // lengths equal to zero. For the
+                                            // basic encryption modes
+                                            // (ECB/CBC/CTR/ICM/CFB128) it is
+                                            // allowed to program zero to the
+                                            // length field; in that case the
+                                            // length is assumed infinite. All
+                                            // data must be byte (8-bit)
+                                            // aligned; bit aligned data streams
+                                            // are not supported by the AES
+                                            // Engine. For a Host read
+                                            // operation@@ these registers
+                                            // return all-zeroes.
+
+#define AES_C_LENGTH_1_LENGTH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// AES_O_AUTH_LENGTH register.
+//
+//******************************************************************************
+#define AES_AUTH_LENGTH_AUTH_M \
+                                0xFFFFFFFF  // data
+
+#define AES_AUTH_LENGTH_AUTH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_0 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_0_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
+#define AES_DATA_IN_0_DATA_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_1 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_1_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
+#define AES_DATA_IN_1_DATA_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_2 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_2_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
+#define AES_DATA_IN_2_DATA_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_3 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_3_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
+#define AES_DATA_IN_3_DATA_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_0_HASH_M  0xFFFFFFFF  // Hash result (MSW)
+#define AES_TAG_OUT_0_HASH_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_1_HASH_M  0xFFFFFFFF  // Hash result (MSW)
+#define AES_TAG_OUT_1_HASH_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_2_HASH_M  0xFFFFFFFF  // Hash result (MSW)
+#define AES_TAG_OUT_2_HASH_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_3_HASH_M  0xFFFFFFFF  // Hash result (LSW)
+#define AES_TAG_OUT_3_HASH_S  0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_REVISION register.
+//
+//******************************************************************************
+#define AES_REVISION_SCHEME_M 0xC0000000
+#define AES_REVISION_SCHEME_S 30
+#define AES_REVISION_FUNC_M   0x0FFF0000  // Function indicates a software
+                                            // compatible module family. If
+                                            // there is no level of software
+                                            // compatibility a new Func number
+                                            // (and hence REVISION) should be
+                                            // assigned.
+#define AES_REVISION_FUNC_S   16
+#define AES_REVISION_R_RTL_M  0x0000F800  // RTL Version (R)@@ maintained by
+                                            // IP design owner. RTL follows a
+                                            // numbering such as X.Y.R.Z which
+                                            // are explained in this table. R
+                                            // changes ONLY when: (1) PDS
+                                            // uploads occur which may have been
+                                            // due to spec changes (2) Bug fixes
+                                            // occur (3) Resets to '0' when X or
+                                            // Y changes. Design team has an
+                                            // internal 'Z' (customer invisible)
+                                            // number which increments on every
+                                            // drop that happens due to DV and
+                                            // RTL updates. Z resets to 0 when R
+                                            // increments.
+#define AES_REVISION_R_RTL_S  11
+#define AES_REVISION_X_MAJOR_M \
+                                0x00000700  // Major Revision (X)@@ maintained
+                                            // by IP specification owner. X
+                                            // changes ONLY when: (1) There is a
+                                            // major feature addition. An
+                                            // example would be adding Master
+                                            // Mode to Utopia Level2. The Func
+                                            // field (or Class/Type in old PID
+                                            // format) will remain the same. X
+                                            // does NOT change due to: (1) Bug
+                                            // fixes (2) Change in feature
+                                            // parameters.
+
+#define AES_REVISION_X_MAJOR_S 8
+#define AES_REVISION_CUSTOM_M 0x000000C0
+#define AES_REVISION_CUSTOM_S 6
+#define AES_REVISION_Y_MINOR_M \
+                                0x0000003F  // Minor Revision (Y)@@ maintained
+                                            // by IP specification owner. Y
+                                            // changes ONLY when: (1) Features
+                                            // are scaled (up or down).
+                                            // Flexibility exists in that this
+                                            // feature scalability may either be
+                                            // represented in the Y change or a
+                                            // specific register in the IP that
+                                            // indicates which features are
+                                            // exactly available. (2) When
+                                            // feature creeps from Is-Not list
+                                            // to Is list. But this may not be
+                                            // the case once it sees silicon; in
+                                            // which case X will change. Y does
+                                            // NOT change due to: (1) Bug fixes
+                                            // (2) Typos or clarifications (3)
+                                            // major functional/feature
+                                            // change/addition/deletion. Instead
+                                            // these changes may be reflected
+                                            // via R@@ S@@ X as applicable. Spec
+                                            // owner maintains a
+                                            // customer-invisible number 'S'
+                                            // which changes due to: (1)
+                                            // Typos/clarifications (2) Bug
+                                            // documentation. Note that this bug
+                                            // is not due to a spec change but
+                                            // due to implementation.
+                                            // Nevertheless@@ the spec tracks
+                                            // the IP bugs. An RTL release (say
+                                            // for silicon PG1.1) that occurs
+                                            // due to bug fix should document
+                                            // the corresponding spec number
+                                            // (X.Y.S) in its release notes.
+
+#define AES_REVISION_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \
+                                0x00000200  // If set to '1' the two context
+                                            // out requests
+                                            // (dma_req_context_out_en@@ Bit [8]
+                                            // above@@ and context_out interrupt
+                                            // enable@@ Bit [3] of AES_IRQENABLE
+                                            // register) are mapped on the
+                                            // corresponding data output request
+                                            // bit. In this case@@ the original
+                                            // ‘context out’ bit values are
+                                            // ignored.
+
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
+                                0x00000100  // If set to ‘1’@@ the DMA context
+                                            // output request is enabled (for
+                                            // context data out@@ e.g. TAG for
+                                            // authentication modes). 0 Dma
+                                            // disabled 1 Dma enabled
+
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
+                                0x00000080  // If set to ‘1’@@ the DMA context
+                                            // request is enabled. 0 Dma
+                                            // disabled 1 Dma enabled
+
+#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
+                                0x00000040  // If set to ‘1’@@ the DMA output
+                                            // request is enabled. 0 Dma
+                                            // disabled 1 Dma enabled
+
+#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
+                                0x00000020  // If set to ‘1’@@ the DMA input
+                                            // request is enabled. 0 Dma
+                                            // disabled 1 Dma enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define AES_SYSSTATUS_RESETDONE \
+                                0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQSTATUS register.
+//
+//******************************************************************************
+#define AES_IRQSTATUS_CONTEXT_OUT \
+                                0x00000008  // This bit indicates
+                                            // authentication tag (and IV)
+                                            // interrupt(s) is/are active and
+                                            // triggers the interrupt output.
+
+#define AES_IRQSTATUS_DATA_OUT \
+                                0x00000004  // This bit indicates data output
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+
+#define AES_IRQSTATUS_DATA_IN 0x00000002  // This bit indicates data input
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+#define AES_IRQSTATUS_CONTEX_IN \
+                                0x00000001  // This bit indicates context
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQENABLE register.
+//
+//******************************************************************************
+#define AES_IRQENABLE_CONTEXT_OUT \
+                                0x00000008  // This bit indicates
+                                            // authentication tag (and IV)
+                                            // interrupt(s) is/are active and
+                                            // triggers the interrupt output.
+
+#define AES_IRQENABLE_DATA_OUT \
+                                0x00000004  // This bit indicates data output
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+
+#define AES_IRQENABLE_DATA_IN 0x00000002  // This bit indicates data input
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+#define AES_IRQENABLE_CONTEX_IN \
+                                0x00000001  // This bit indicates context
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+
+
+
+
+#endif // __HW_AES_H__

cc3200/hal/inc/hw_apps_config.h

@@ -0,0 +1,747 @@
+//*****************************************************************************
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+
+#ifndef __HW_APPS_CONFIG_H__
+#define __HW_APPS_CONFIG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the APPS_CONFIG register offsets.
+//
+//*****************************************************************************
+#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \
+                                0x00000000  // Patch trap address Register
+                                            // array
+
+#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \
+                                0x00000078
+
+#define APPS_CONFIG_O_FAULT_STATUS_REG \
+                                0x0000007C
+
+#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \
+                                0x00000080
+
+#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \
+                                0x00000084
+
+#define APPS_CONFIG_O_DMA_DONE_INT_MASK \
+                                0x0000008C
+
+#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \
+                                0x00000090
+
+#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \
+                                0x00000094
+
+#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \
+                                0x00000098
+
+#define APPS_CONFIG_O_DMA_DONE_INT_ACK \
+                                0x0000009C
+
+#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \
+                                0x000000A0
+
+#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \
+                                0x000000A4
+
+#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \
+                                0x000000A8
+
+#define APPS_CONFIG_O_RESERVD_REG_0 \
+                                0x000000AC
+
+#define APPS_CONFIG_O_GPT_TRIG_SEL \
+                                0x000000B0
+
+#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \
+                                0x000000B4
+
+#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \
+                                0x000000B8
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \
+                                0xFFFFFFFF  // When PATCH_TRAP_EN[n] is set bus
+                                            // fault is generated for the
+                                            // address
+                                            // PATCH_TRAP_ADDR_REG[n][31:0] from
+                                            // Idcode bus. The exception routine
+                                            // should take care to jump to the
+                                            // location where the patch
+                                            // correspond to this address is
+                                            // kept.
+
+#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_PATCH_TRAP_EN_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \
+                                0x3FFFFFFF  // When PATCH_TRAP_EN[n] is set bus
+                                            // fault is generated for the
+                                            // address PATCH_TRAP_ADD[n][31:0]
+                                            // from Idcode bus. The exception
+                                            // routine should take care to jump
+                                            // to the location where the patch
+                                            // correspond to this address is
+                                            // kept.
+
+#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_FAULT_STATUS_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \
+                                0x0000003E  // This field shows because of
+                                            // which patch trap address the
+                                            // bus_fault is generated. If the
+                                            // PATCH_ERR bit is set, then it
+                                            // means the bus fault is generated
+                                            // because of
+                                            // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX]
+
+#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1
+#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \
+                                0x00000001  // This bit is set when there is a
+                                            // bus fault because of patched
+                                            // address access to the Apps boot
+                                            // rom. Write 0 to clear this
+                                            // register.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \
+                                0x00000001  // This bit is set when there is a
+                                            // an error in memss write access.
+                                            // And the address causing this
+                                            // error is captured in
+                                            // MEMSS_ERR_ADDR_REG. To capture
+                                            // the next error address one have
+                                            // to clear this bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_MASK register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \
+                                0x0000F000  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+                                            // bit 14: ADC channel 7 interrupt
+                                            // enable/disable bit 13: ADC
+                                            // channel 5 interrupt
+                                            // enable/disable bit 12: ADC
+                                            // channel 3 interrupt
+                                            // enable/disable bit 11: ADC
+                                            // channel 1 interrupt
+                                            // enable/disable
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12
+#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \
+                                0x00000800  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \
+                                0x00000400  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \
+                                0x00000200  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \
+                                0x00000100  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \
+                                0x00000080  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \
+                                0x00000040  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \
+                                0x00000020  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \
+                                0x00000010  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \
+                                0x00000008  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \
+                                0x00000004  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \
+                                0x00000002  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \
+                                0x00000001  // 1= disable corresponding
+                                            // interrupt;0 = interrupt enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \
+                                0x0000F000  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect bit 14: ADC channel 7 DMA
+                                            // Done IRQ bit 13: ADC channel 5
+                                            // DMA Done IRQ bit 12: ADC channel
+                                            // 3 DMA Done IRQ bit 11: ADC
+                                            // channel 1 DMA Done IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \
+                                0x00000800  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \
+                                0x00000400  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \
+                                0x00000200  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \
+                                0x00000100  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \
+                                0x00000080  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \
+                                0x00000040  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \
+                                0x00000020  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \
+                                0x00000010  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \
+                                0x00000008  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \
+                                0x00000004  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \
+                                0x00000002  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \
+                                0x00000001  // write 1 to set mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \
+                                0x0000F000  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect bit 14: ADC channel 7 DMA
+                                            // Done IRQ mask bit 13: ADC channel
+                                            // 5 DMA Done IRQ mask bit 12: ADC
+                                            // channel 3 DMA Done IRQ mask bit
+                                            // 11: ADC channel 1 DMA Done IRQ
+                                            // mask
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \
+                                0x00000800  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \
+                                0x00000400  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \
+                                0x00000200  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \
+                                0x00000100  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \
+                                0x00000080  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \
+                                0x00000040  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \
+                                0x00000020  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \
+                                0x00000010  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \
+                                0x00000008  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \
+                                0x00000004  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \
+                                0x00000002  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \
+                                0x00000001  // write 1 to clear mask of the
+                                            // corresponding DMA DONE IRQ;0 = no
+                                            // effect
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \
+                                0xFFFFFFFF  // write 1 or 0 to clear all
+                                            // DMA_DONE interrupt;
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_ACK register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \
+                                0x0000F000  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect; bit 14:
+                                            // ADC channel 7 DMA Done IRQ bit
+                                            // 13: ADC channel 5 DMA Done IRQ
+                                            // bit 12: ADC channel 3 DMA Done
+                                            // IRQ bit 11: ADC channel 1 DMA
+                                            // Done IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12
+#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \
+                                0x00000800  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \
+                                0x00000400  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \
+                                0x00000200  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \
+                                0x00000100  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \
+                                0x00000080  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \
+                                0x00000040  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \
+                                0x00000020  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \
+                                0x00000010  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \
+                                0x00000008  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \
+                                0x00000004  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \
+                                0x00000002  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \
+                                0x00000001  // write 1 to clear corresponding
+                                            // interrupt; 0 = no effect;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \
+                                0x0000F000  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask bit 14: ADC
+                                            // channel 7 DMA Done IRQ bit 13:
+                                            // ADC channel 5 DMA Done IRQ bit
+                                            // 12: ADC channel 3 DMA Done IRQ
+                                            // bit 11: ADC channel 1 DMA Done
+                                            // IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \
+                                0x00000800  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \
+                                0x00000400  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \
+                                0x00000200  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \
+                                0x00000100  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \
+                                0x00000080  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \
+                                0x00000040  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \
+                                0x00000020  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \
+                                0x00000010  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \
+                                0x00000008  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \
+                                0x00000004  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \
+                                0x00000002  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \
+                                0x00000001  // 1= corresponding interrupt is
+                                            // active and not masked. read is
+                                            // non-destructive;0 = corresponding
+                                            // interrupt is inactive or masked
+                                            // by DMA_DONE_INT mask
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \
+                                0x0000F000  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive bit 14: ADC channel 7
+                                            // DMA Done IRQ bit 13: ADC channel
+                                            // 5 DMA Done IRQ bit 12: ADC
+                                            // channel 3 DMA Done IRQ bit 11:
+                                            // ADC channel 1 DMA Done IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \
+                                0x00000800  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \
+                                0x00000400  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \
+                                0x00000200  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \
+                                0x00000100  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \
+                                0x00000080  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \
+                                0x00000040  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \
+                                0x00000020  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \
+                                0x00000010  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \
+                                0x00000008  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \
+                                0x00000004  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \
+                                0x00000002  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \
+                                0x00000001  // 1= corresponding interrupt is
+                                            // active. read is non-destructive;0
+                                            // = corresponding interrupt is
+                                            // inactive
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \
+                                0x00000001  // Write 1 to clear the LSB of
+                                            // FAULT_STATUS_REG
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_RESERVD_REG_0 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_GPT_TRIG_SEL register.
+//
+//******************************************************************************
+#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \
+                                0x000000FF  // This bit is implemented for GPT
+                                            // trigger mode select. GPT IP
+                                            // support 2 modes: RTC mode and
+                                            // external trigger. When this bit
+                                            // is set to logic '1': enable
+                                            // external trigger mode for APPS
+                                            // GPT CP0 and CP1 pin. bit 0: when
+                                            // set '1' enable external GPT
+                                            // trigger 0 on GPIO0 CP0 pin else
+                                            // RTC mode is selected. bit 1: when
+                                            // set '1' enable external GPT
+                                            // trigger 1 on GPIO0 CP1 pin else
+                                            // RTC mode is selected. bit 2: when
+                                            // set '1' enable external GPT
+                                            // trigger 2 on GPIO1 CP0 pin else
+                                            // RTC mode is selected. bit 3: when
+                                            // set '1' enable external GPT
+                                            // trigger 3 on GPIO1 CP1 pin else
+                                            // RTC mode is selected. bit 4: when
+                                            // set '1' enable external GPT
+                                            // trigger 4 on GPIO2 CP0 pin else
+                                            // RTC mode is selected. bit 5: when
+                                            // set '1' enable external GPT
+                                            // trigger 5 on GPIO2 CP1 pin else
+                                            // RTC mode is selected. bit 6: when
+                                            // set '1' enable external GPT
+                                            // trigger 6 on GPIO3 CP0 pin else
+                                            // RTC mode is selected. bit 7: when
+                                            // set '1' enable external GPT
+                                            // trigger 7 on GPIO3 CP1 pin else
+                                            // RTC mode is selected.
+
+#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \
+                                0x00000007  // Capture data from d2d_spare pads
+
+#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \
+                                0x00000007  // Send data to d2d_spare pads -
+                                            // eventually this will get
+                                            // registered in top die
+
+#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0
+
+
+
+#endif // __HW_APPS_CONFIG_H__

cc3200/hal/inc/hw_camera.h

@@ -0,0 +1,519 @@
+//*****************************************************************************
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAMERA_H__
+#define __HW_CAMERA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAMERA register offsets.
+//
+//*****************************************************************************
+#define CAMERA_O_CC_REVISION    0x00000000  // This register contains the IP
+                                            // revision code ( Parallel Mode)
+#define CAMERA_O_CC_SYSCONFIG   0x00000010  // This register controls the
+                                            // various parameters of the OCP
+                                            // interface (CCP and Parallel Mode)
+#define CAMERA_O_CC_SYSSTATUS   0x00000014  // This register provides status
+                                            // information about the module
+                                            // excluding the interrupt status
+                                            // information (CCP and Parallel
+                                            // Mode)
+#define CAMERA_O_CC_IRQSTATUS   0x00000018  // The interrupt status regroups
+                                            // all the status of the module
+                                            // internal events that can generate
+                                            // an interrupt (CCP & Parallel
+                                            // Mode)
+#define CAMERA_O_CC_IRQENABLE   0x0000001C  // The interrupt enable register
+                                            // allows to enable/disable the
+                                            // module internal sources of
+                                            // interrupt on an event-by-event
+                                            // basis (CCP & Parallel Mode)
+#define CAMERA_O_CC_CTRL        0x00000040  // This register controls the
+                                            // various parameters of the Camera
+                                            // Core block (CCP & Parallel Mode)
+#define CAMERA_O_CC_CTRL_DMA    0x00000044  // This register controls the DMA
+                                            // interface of the Camera Core
+                                            // block (CCP & Parallel Mode)
+#define CAMERA_O_CC_CTRL_XCLK   0x00000048  // This register control the value
+                                            // of the clock divisor used to
+                                            // generate the external clock
+                                            // (Parallel Mode)
+#define CAMERA_O_CC_FIFO_DATA   0x0000004C  // This register allows to write to
+                                            // the FIFO and read from the FIFO
+                                            // (CCP & Parallel Mode)
+#define CAMERA_O_CC_TEST        0x00000050  // This register shows the status
+                                            // of some important variables of
+                                            // the camera core module (CCP &
+                                            // Parallel Mode)
+#define CAMERA_O_CC_GEN_PAR     0x00000054  // This register shows the values
+                                            // of the generic parameters of the
+                                            // module
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_REVISION register.
+//
+//******************************************************************************
+#define CAMERA_CC_REVISION_REV_M \
+                                0x000000FF  // IP revision [7:4] Major revision
+                                            // [3:0] Minor revision Examples:
+                                            // 0x10 for 1.0 0x21 for 2.1
+
+#define CAMERA_CC_REVISION_REV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_SYSCONFIG register.
+//
+//******************************************************************************
+#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
+                                0x00000018  // Slave interface power management
+                                            // req/ack control """00""
+                                            // Force-idle. An idle request is
+                                            // acknoledged unconditionally"
+                                            // """01"" No-idle. An idle request
+                                            // is never acknowledged" """10""
+                                            // reserved (Smart-idle not
+                                            // implemented)"
+
+#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
+#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
+                                0x00000002  // Software reset. Set this bit to
+                                            // 1 to trigger a module reset. The
+                                            // bit is automatically reset by the
+                                            // hardware. During reset it always
+                                            // returns 0. 0 Normal mode 1 The
+                                            // module is reset
+
+#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
+                                0x00000001  // Internal OCP clock gating
+                                            // strategy 0 OCP clock is
+                                            // free-running 1 Automatic OCP
+                                            // clock gating strategy is applied
+                                            // based on the OCP interface
+                                            // activity
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_SYSSTATUS register.
+//
+//******************************************************************************
+#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
+                                0x00000001  // Internal Reset Monitoring 0
+                                            // Internal module reset is on-going
+                                            // 1 Reset completed
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_IRQSTATUS register.
+//
+//******************************************************************************
+#define CAMERA_CC_IRQSTATUS_FS_IRQ \
+                                0x00080000  // Frame Start has occurred 0 Event
+                                            // false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_LE_IRQ \
+                                0x00040000  // Line End has occurred 0 Event
+                                            // false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_LS_IRQ \
+                                0x00020000  // Line Start has occurred 0 Event
+                                            // false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_FE_IRQ \
+                                0x00010000  // Frame End has occurred 0 Event
+                                            // false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
+                                0x00000800  // FSP code error 0 Event false "1
+                                            // Event is true (""pending"")" 0
+                                            // Event status bit unchanged 1
+                                            // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
+                                0x00000400  // Frame Height Error 0 Event false
+                                            // "1 Event is true (""pending"")" 0
+                                            // Event status bit unchanged 1
+                                            // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
+                                0x00000200  // False Synchronization Code 0
+                                            // Event false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
+                                0x00000100  // Shifted Synchronization Code 0
+                                            // Event false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
+                                0x00000010  // FIFO is not empty 0 Event false
+                                            // "1 Event is true (""pending"")" 0
+                                            // Event status bit unchanged 1
+                                            // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
+                                0x00000008  // FIFO is full 0 Event false "1
+                                            // Event is true (""pending"")" 0
+                                            // Event status bit unchanged 1
+                                            // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
+                                0x00000004  // FIFO threshold has been reached
+                                            // 0 Event false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
+                                0x00000002  // FIFO overflow has occurred 0
+                                            // Event false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
+                                0x00000001  // FIFO underflow has occurred 0
+                                            // Event false "1 Event is true
+                                            // (""pending"")" 0 Event status bit
+                                            // unchanged 1 Event status bit is
+                                            // reset
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_IRQENABLE register.
+//
+//******************************************************************************
+#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
+                                0x00080000  // Frame Start Interrupt Enable 0
+                                            // Event is masked 1 Event generates
+                                            // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
+                                0x00040000  // Line End Interrupt Enable 0
+                                            // Event is masked 1 Event generates
+                                            // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
+                                0x00020000  // Line Start Interrupt Enable 0
+                                            // Event is masked 1 Event generates
+                                            // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
+                                0x00010000  // Frame End Interrupt Enable 0
+                                            // Event is masked 1 Event generates
+                                            // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
+                                0x00000800  // FSP code Interrupt Enable 0
+                                            // Event is masked 1 Event generates
+                                            // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
+                                0x00000400  // Frame Height Error Interrupt
+                                            // Enable 0 Event is masked 1 Event
+                                            // generates an interrupt when it
+                                            // occurs
+
+#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
+                                0x00000200  // False Synchronization Code
+                                            // Interrupt Enable 0 Event is
+                                            // masked 1 Event generates an
+                                            // interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
+                                0x00000100  // False Synchronization Code
+                                            // Interrupt Enable 0 Event is
+                                            // masked 1 Event generates an
+                                            // interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
+                                0x00000010  // FIFO Threshold Interrupt Enable
+                                            // 0 Event is masked 1 Event
+                                            // generates an interrupt when it
+                                            // occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
+                                0x00000008  // FIFO Threshold Interrupt Enable
+                                            // 0 Event is masked 1 Event
+                                            // generates an interrupt when it
+                                            // occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
+                                0x00000004  // FIFO Threshold Interrupt Enable
+                                            // 0 Event is masked 1 Event
+                                            // generates an interrupt when it
+                                            // occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
+                                0x00000002  // FIFO Overflow Interrupt Enable 0
+                                            // Event is masked 1 Event generates
+                                            // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
+                                0x00000001  // FIFO Underflow Interrupt Enable
+                                            // 0 Event is masked 1 Event
+                                            // generates an interrupt when it
+                                            // occurs
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
+//
+//******************************************************************************
+#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
+                                0x00080000  // Synchronize all camera sensor
+                                            // inputs This must be set during
+                                            // the configuration phase before
+                                            // CC_EN set to '1'. This can be
+                                            // used in very high frequency to
+                                            // avoid dependancy to the IO
+                                            // timings. 0 No synchro (most of
+                                            // applications) 1 Synchro enabled
+                                            // (should never be required)
+
+#define CAMERA_CC_CTRL_CC_RST   0x00040000  // Resets all the internal finite
+                                            // states machines of the camera
+                                            // core module - by writing a 1 to
+                                            // this bit. must be applied when
+                                            // CC_EN = 0 Reads returns 0
+#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
+                                0x00020000  // Set the modality in which CC_EN
+                                            // works when a disabling of the
+                                            // sensor camera core is wanted "If
+                                            // CC_FRAME_TRIG = 1 by writing
+                                            // ""0"" to CC_EN" the module is
+                                            // disabled at the end of the frame
+                                            // "If CC_FRAME_TRIG = 0 by writing
+                                            // ""0"" to CC_EN" the module is
+                                            // disabled immediately
+
+#define CAMERA_CC_CTRL_CC_EN    0x00010000  // Enables the sensor interface of
+                                            // the camera core module "By
+                                            // writing ""1"" to this field the
+                                            // module is enabled." "By writing
+                                            // ""0"" to this field the module is
+                                            // disabled at" the end of the frame
+                                            // if CC_FRAM_TRIG =1 and is
+                                            // disabled immediately if
+                                            // CC_FRAM_TRIG = 0
+#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
+                                0x00002000  // Enables to start at the
+                                            // beginning of the frame or not in
+                                            // NoBT 0 Acquisition starts when
+                                            // Vertical synchro is high 1
+                                            // Acquisition starts when Vertical
+                                            // synchro goes from low to high
+                                            // (beginning of the frame) -
+                                            // Recommended.
+
+#define CAMERA_CC_CTRL_BT_CORRECT \
+                                0x00001000  // Enables the correction within
+                                            // the sync codes in BT mode 0
+                                            // correction is not enabled 1
+                                            // correction is enabled
+
+#define CAMERA_CC_CTRL_PAR_ORDERCAM \
+                                0x00000800  // Enables swap between image-data
+                                            // in parallel mode 0 swap is not
+                                            // enabled 1 swap is enabled
+
+#define CAMERA_CC_CTRL_PAR_CLK_POL \
+                                0x00000400  // Inverts the clock coming from
+                                            // the sensor in parallel mode 0
+                                            // clock not inverted - data sampled
+                                            // on rising edge 1 clock inverted -
+                                            // data sampled on falling edge
+
+#define CAMERA_CC_CTRL_NOBT_HS_POL \
+                                0x00000200  // Sets the polarity of the
+                                            // synchronization signals in NOBT
+                                            // parallel mode 0 CAM_P_HS is
+                                            // active high 1 CAM_P_HS is active
+                                            // low
+
+#define CAMERA_CC_CTRL_NOBT_VS_POL \
+                                0x00000100  // Sets the polarity of the
+                                            // synchronization signals in NOBT
+                                            // parallel mode 0 CAM_P_VS is
+                                            // active high 1 CAM_P_VS is active
+                                            // low
+
+#define CAMERA_CC_CTRL_PAR_MODE_M \
+                                0x0000000E  // Sets the Protocol Mode of the
+                                            // Camera Core module in parallel
+                                            // mode (when CCP_MODE = 0) """000""
+                                            // Parallel NOBT 8-bit" """001""
+                                            // Parallel NOBT 10-bit" """010""
+                                            // Parallel NOBT 12-bit" """011""
+                                            // reserved" """100"" Parallet BT
+                                            // 8-bit" """101"" Parallel BT
+                                            // 10-bit" """110"" reserved"
+                                            // """111"" FIFO test mode. Refer to
+                                            // Table 12 - FIFO Write and Read
+                                            // access"
+
+#define CAMERA_CC_CTRL_PAR_MODE_S 1
+#define CAMERA_CC_CTRL_CCP_MODE 0x00000001  // Set the Camera Core in CCP mode
+                                            // 0 CCP mode disabled 1 CCP mode
+                                            // enabled
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_CTRL_DMA register.
+//
+//******************************************************************************
+#define CAMERA_CC_CTRL_DMA_DMA_EN \
+                                0x00000100  // Sets the number of dma request
+                                            // lines 0 DMA interface disabled
+                                            // The DMA request line stays
+                                            // inactive 1 DMA interface enabled
+                                            // The DMA request line is
+                                            // operational
+
+#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
+                                0x0000007F  // Sets the threshold of the FIFO
+                                            // the assertion of the dmarequest
+                                            // line takes place when the
+                                            // threshold is reached.
+                                            // """0000000"" threshold set to 1"
+                                            // """0000001"" threshold set to 2"
+                                            // … """1111111"" threshold set to
+                                            // 128"
+
+#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_CTRL_XCLK register.
+//
+//******************************************************************************
+#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
+                                0x0000001F  // Sets the clock divisor value for
+                                            // CAM_XCLK generation. based on
+                                            // CAM_MCK (value of CAM_MCLK is
+                                            // 96MHz) """00000"" CAM_XCLK Stable
+                                            // Low Level" Divider not enabled
+                                            // """00001"" CAM_XCLK Stable High
+                                            // Level" Divider not enabled from 2
+                                            // to 30 CAM_XCLK = CAM_MCLK /
+                                            // XCLK_DIV """11111"" Bypass -
+                                            // CAM_XCLK = CAM_MCLK"
+
+#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_FIFO_DATA register.
+//
+//******************************************************************************
+#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
+                                0xFFFFFFFF  // Writes the 32-bit word into the
+                                            // FIFO Reads the 32-bit word from
+                                            // the FIFO
+
+#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
+//
+//******************************************************************************
+#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
+                                0xFF000000  // FIFO READ Pointer This field
+                                            // shows the value of the FIFO read
+                                            // pointer Expected value ranges
+                                            // from 0 to 127
+
+#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
+#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
+                                0x00FF0000  // FIFO WRITE pointer This field
+                                            // shows the value of the FIFO write
+                                            // pointer Expected value ranges
+                                            // from 0 to 127
+
+#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
+#define CAMERA_CC_TEST_FIFO_LEVEL_M \
+                                0x0000FF00  // FIFO level (how many 32-bit
+                                            // words the FIFO contains) This
+                                            // field shows the value of the FIFO
+                                            // level and can assume values from
+                                            // 0 to 128
+
+#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
+#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
+                                0x000000FF  // FIFO level peak This field shows
+                                            // the max value of the FIFO level
+                                            // and can assume values from 0 to
+                                            // 128
+
+#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_GEN_PAR register.
+//
+//******************************************************************************
+#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
+                                0x00000007  // Camera Core FIFO DEPTH generic
+                                            // parameter
+
+#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
+
+
+
+#endif // __HW_CAMERA_H__

cc3200/hal/inc/hw_des.h

@@ -0,0 +1,339 @@
+//*****************************************************************************
+//
+//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions
+//  are met:
+//
+//    Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+//    Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the
+//    distribution.
+//
+//    Neither the name of Texas Instruments Incorporated nor the names of
+//    its contributors may be used to endorse or promote products derived
+//    from this software without specific prior written permission.
+//
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_DES_H__
+#define __HW_DES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the DES_P register offsets.
+//
+//*****************************************************************************
+#define DES_O_KEY3_L          0x00000000  // KEY3 (LSW) for 192-bit key
+#define DES_O_KEY3_H          0x00000004  // KEY3 (MSW) for 192-bit key
+#define DES_O_KEY2_L          0x00000008  // KEY2 (LSW) for 192-bit key
+#define DES_O_KEY2_H          0x0000000C  // KEY2 (MSW) for 192-bit key
+#define DES_O_KEY1_L          0x00000010  // KEY1 (LSW) for 128-bit
+                                            // key/192-bit key
+#define DES_O_KEY1_H          0x00000014  // KEY1 (LSW) for 128-bit
+                                            // key/192-bit key
+#define DES_O_IV_L            0x00000018  // Initialization vector LSW
+#define DES_O_IV_H            0x0000001C  // Initialization vector MSW
+#define DES_O_CTRL            0x00000020
+#define DES_O_LENGTH          0x00000024  // Indicates the cryptographic data
+                                            // length in bytes for all modes.
+                                            // Once processing is started with
+                                            // this context this length
+                                            // decrements to zero. Data lengths
+                                            // up to (2^32 – 1) bytes are
+                                            // allowed. A write to this register
+                                            // triggers the engine to start
+                                            // using this context. For a Host
+                                            // read operation these registers
+                                            // return all-zeroes.
+#define DES_O_DATA_L          0x00000028  // Data register(LSW) to read/write
+                                            // encrypted/decrypted data.
+#define DES_O_DATA_H          0x0000002C  // Data register(MSW) to read/write
+                                            // encrypted/decrypted data.
+#define DES_O_REVISION        0x00000030
+#define DES_O_SYSCONFIG       0x00000034
+#define DES_O_SYSSTATUS       0x00000038
+#define DES_O_IRQSTATUS       0x0000003C  // This register indicates the
+                                            // interrupt status. If one of the
+                                            // interrupt bits is set the
+                                            // interrupt output will be asserted
+#define DES_O_IRQENABLE       0x00000040  // This register contains an enable
+                                            // bit for each unique interrupt
+                                            // generated by the module. It
+                                            // matches the layout of
+                                            // DES_IRQSTATUS register. An
+                                            // interrupt is enabled when the bit
+                                            // in this register is set to 1
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_L register.
+//
+//******************************************************************************
+#define DES_KEY3_L_KEY3_L_M   0xFFFFFFFF  // data for key3
+#define DES_KEY3_L_KEY3_L_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_H register.
+//
+//******************************************************************************
+#define DES_KEY3_H_KEY3_H_M   0xFFFFFFFF  // data for key3
+#define DES_KEY3_H_KEY3_H_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_L register.
+//
+//******************************************************************************
+#define DES_KEY2_L_KEY2_L_M   0xFFFFFFFF  // data for key2
+#define DES_KEY2_L_KEY2_L_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_H register.
+//
+//******************************************************************************
+#define DES_KEY2_H_KEY2_H_M   0xFFFFFFFF  // data for key2
+#define DES_KEY2_H_KEY2_H_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_L register.
+//
+//******************************************************************************
+#define DES_KEY1_L_KEY1_L_M   0xFFFFFFFF  // data for key1
+#define DES_KEY1_L_KEY1_L_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_H register.
+//
+//******************************************************************************
+#define DES_KEY1_H_KEY1_H_M   0xFFFFFFFF  // data for key1
+#define DES_KEY1_H_KEY1_H_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_L register.
+//
+//******************************************************************************
+#define DES_IV_L_IV_L_M       0xFFFFFFFF  // initialization vector for CBC
+                                            // CFB modes
+#define DES_IV_L_IV_L_S       0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_H register.
+//
+//******************************************************************************
+#define DES_IV_H_IV_H_M       0xFFFFFFFF  // initialization vector for CBC
+                                            // CFB modes
+#define DES_IV_H_IV_H_S       0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_CTRL register.
+//
+//******************************************************************************
+#define DES_CTRL_CONTEXT      0x80000000  // If ‘1’ this read-only status bit
+                                            // indicates that the context data
+                                            // registers can be overwritten and
+                                            // the host is permitted to write
+                                            // the next context.
+#define DES_CTRL_MODE_M       0x00000030  // Select CBC ECB or CFB mode 0x0
+                                            // ecb mode 0x1 cbc mode 0x2 cfb
+                                            // mode 0x3 reserved
+#define DES_CTRL_MODE_S       4
+#define DES_CTRL_TDES         0x00000008  // Select DES or triple DES
+                                            // encryption/decryption. 0 des mode
+                                            // 1 tdes mode
+#define DES_CTRL_DIRECTION    0x00000004  // select encryption/decryption 0
+                                            // decryption is selected 1
+                                            // Encryption is selected
+#define DES_CTRL_INPUT_READY  0x00000002  // When '1' ready to
+                                            // encrypt/decrypt data
+#define DES_CTRL_OUTPUT_READY 0x00000001  // When '1' Data
+                                            // decrypted/encrypted ready
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_LENGTH register.
+//
+//******************************************************************************
+#define DES_LENGTH_LENGTH_M   0xFFFFFFFF
+#define DES_LENGTH_LENGTH_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_L register.
+//
+//******************************************************************************
+#define DES_DATA_L_DATA_L_M   0xFFFFFFFF  // data for encryption/decryption
+#define DES_DATA_L_DATA_L_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_H register.
+//
+//******************************************************************************
+#define DES_DATA_H_DATA_H_M   0xFFFFFFFF  // data for encryption/decryption
+#define DES_DATA_H_DATA_H_S   0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_REVISION register.
+//
+//******************************************************************************
+#define DES_REVISION_SCHEME_M 0xC0000000
+#define DES_REVISION_SCHEME_S 30
+#define DES_REVISION_FUNC_M   0x0FFF0000  // Function indicates a software
+                                            // compatible module family. If
+                                            // there is no level of software
+                                            // compatibility a new Func number
+                                            // (and hence REVISION) should be
+                                            // assigned.
+#define DES_REVISION_FUNC_S   16
+#define DES_REVISION_R_RTL_M  0x0000F800  // RTL Version (R) maintained by IP
+                                            // design owner. RTL follows a
+                                            // numbering such as X.Y.R.Z which
+                                            // are explained in this table. R
+                                            // changes ONLY when: (1) PDS
+                                            // uploads occur which may have been
+                                            // due to spec changes (2) Bug fixes
+                                            // occur (3) Resets to '0' when X or
+                                            // Y changes. Design team has an
+                                            // internal 'Z' (customer invisible)
+                                            // number which increments on every
+                                            // drop that happens due to DV and
+                                            // RTL updates. Z resets to 0 when R
+                                            // increments.
+#define DES_REVISION_R_RTL_S  11
+#define DES_REVISION_X_MAJOR_M \
+                                0x00000700  // Major Revision (X) maintained by
+                                            // IP specification owner. X changes
+                                            // ONLY when: (1) There is a major
+                                            // feature addition. An example
+                                            // would be adding Master Mode to
+                                            // Utopia Level2. The Func field (or
+                                            // Class/Type in old PID format)
+                                            // will remain the same. X does NOT
+                                            // change due to: (1) Bug fixes (2)
+                                            // Change in feature parameters.
+
+#define DES_REVISION_X_MAJOR_S 8
+#define DES_REVISION_CUSTOM_M 0x000000C0
+#define DES_REVISION_CUSTOM_S 6
+#define DES_REVISION_Y_MINOR_M \
+                                0x0000003F  // Minor Revision (Y) maintained by
+                                            // IP specification owner. Y changes
+                                            // ONLY when: (1) Features are
+                                            // scaled (up or down). Flexibility
+                                            // exists in that this feature
+                                            // scalability may either be
+                                            // represented in the Y change or a
+                                            // specific register in the IP that
+                                            // indicates which features are
+                                            // exactly available. (2) When
+                                            // feature creeps from Is-Not list
+                                            // to Is list. But this may not be
+                                            // the case once it sees silicon; in
+                                            // which case X will change. Y does
+                                            // NOT change due to: (1) Bug fixes
+                                            // (2) Typos or clarifications (3)
+                                            // major functional/feature
+                                            // change/addition/deletion. Instead
+                                            // these changes may be reflected
+                                            // via R S X as applicable. Spec
+                                            // owner maintains a
+                                            // customer-invisible number 'S'
+                                            // which changes due to: (1)
+                                            // Typos/clarifications (2) Bug
+                                            // documentation. Note that this bug
+                                            // is not due to a spec change but
+                                            // due to implementation.
+                                            // Nevertheless the spec tracks the
+                                            // IP bugs. An RTL release (say for
+                                            // silicon PG1.1) that occurs due to
+                                            // bug fix should document the
+                                            // corresponding spec number (X.Y.S)
+                                            // in its release notes.
+
+#define DES_REVISION_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
+                                0x00000080  // If set to ‘1’ the DMA context
+                                            // request is enabled. 0 Dma
+                                            // disabled 1 Dma enabled
+
+#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
+                                0x00000040  // If set to ‘1’ the DMA output
+                                            // request is enabled. 0 Dma
+                                            // disabled 1 Dma enabled
+
+#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
+                                0x00000020  // If set to ‘1’ the DMA input
+                                            // request is enabled. 0 Dma
+                                            // disabled 1 Dma enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define DES_SYSSTATUS_RESETDONE \
+                                0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQSTATUS register.
+//
+//******************************************************************************
+#define DES_IRQSTATUS_DATA_OUT \
+                                0x00000004  // This bit indicates data output
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+
+#define DES_IRQSTATUS_DATA_IN 0x00000002  // This bit indicates data input
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+#define DES_IRQSTATUS_CONTEX_IN \
+                                0x00000001  // This bit indicates context
+                                            // interrupt is active and triggers
+                                            // the interrupt output.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQENABLE register.
+//
+//******************************************************************************
+#define DES_IRQENABLE_M_DATA_OUT \
+                                0x00000004  // If this bit is set to ‘1’ the
+                                            // secure data output interrupt is
+                                            // enabled.
+
+#define DES_IRQENABLE_M_DATA_IN \
+                                0x00000002  // If this bit is set to ‘1’ the
+                                            // secure data input interrupt is
+                                            // enabled.
+
+#define DES_IRQENABLE_M_CONTEX_IN \
+                                0x00000001  // If this bit is set to ‘1’ the
+                                            // secure context interrupt is
+                                            // enabled.
+
+
+
+
+#endif // __HW_DES_H__