mirror of
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303 lines
10 KiB
C
303 lines
10 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 OpenMV LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include ALIF_CMSIS_H
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#include "ospi_ext.h"
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#include "ospi_xip_user.h"
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static void ospi_xip_disable(ospi_flash_cfg_t *ospi_cfg) {
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ospi_cfg->aes_regs->aes_control &= ~AES_CONTROL_XIP_EN;
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}
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static void ospi_xip_enable(ospi_flash_cfg_t *ospi_cfg) {
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ospi_cfg->aes_regs->aes_control |= AES_CONTROL_XIP_EN;
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#if OSPI_XIP_ENABLE_AES_DECRYPTION
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ospi_cfg->aes_regs->aes_control |= (AES_CONTROL_LD_KEY | AES_CONTROL_DECRYPT_EN);
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#endif
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}
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// Standard SPI transfer.
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void ospi_spi_transfer(ospi_flash_cfg_t *ospi_cfg, size_t len, const uint8_t *buf_out, uint8_t *buf_in) {
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ospi_writel(ospi_cfg, ser, 0);
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spi_disable(ospi_cfg);
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uint32_t ctrlr0 = CTRLR0_IS_MST
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| (SINGLE << CTRLR0_SPI_FRF_OFFSET)
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| (SPI_TMOD_TR << CTRLR0_TMOD_OFFSET)
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| (CTRLR0_DFS_8bit << CTRLR0_DFS_OFFSET)
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;
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uint32_t spi_ctrlr0 = TRANS_TYPE_STANDARD;
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ospi_writel(ospi_cfg, ctrlr0, ctrlr0);
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ospi_writel(ospi_cfg, ctrlr1, len - 1);
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ospi_writel(ospi_cfg, spi_ctrlr0, spi_ctrlr0);
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spi_enable(ospi_cfg);
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// Buffer output data in SPI FIFO.
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for (int i = 0; i < len; ++i) {
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ospi_writel(ospi_cfg, data_reg, buf_out[i]);
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}
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// Enable the SPI peripheral.
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ospi_writel(ospi_cfg, ser, ospi_cfg->ser);
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// Read in data.
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for (int i = 0; i < len; ++i) {
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unsigned int timeout = 100000;
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while (ospi_readl(ospi_cfg, rxflr) == 0) {
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if (--timeout == 0) {
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return;
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}
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}
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buf_in[i] = ospi_readl(ospi_cfg, data_reg);
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}
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}
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void ospi_setup_read_ext(ospi_flash_cfg_t *ospi_cfg, bool rxds, uint32_t inst_len, uint32_t addr_len, uint32_t data_len, uint32_t read_len, uint32_t wait_cycles) {
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ospi_writel(ospi_cfg, ser, 0);
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spi_disable(ospi_cfg);
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uint32_t val = CTRLR0_IS_MST
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| (OCTAL << CTRLR0_SPI_FRF_OFFSET)
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| (TMOD_RO << CTRLR0_TMOD_OFFSET)
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| (data_len << CTRLR0_DFS_OFFSET);
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ospi_writel(ospi_cfg, ctrlr0, val);
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ospi_writel(ospi_cfg, ctrlr1, read_len - 1);
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if (ospi_cfg->ddr_en) {
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val = TRANS_TYPE_FRF_DEFINED
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| (rxds << CTRLR0_SPI_RXDS_EN_OFFSET)
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| (1 << CTRLR0_SPI_DDR_EN_OFFSET)
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| (inst_len << CTRLR0_INST_L_OFFSET)
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| (addr_len << CTRLR0_ADDR_L_OFFSET)
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| (wait_cycles << CTRLR0_WAIT_CYCLES_OFFSET);
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if (inst_len == OSPI_INST_L_16bit) {
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val |= 1 << CTRLR0_INST_DDR_EN_OFFSET;
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}
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} else {
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val = TRANS_TYPE_FRF_DEFINED
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| (rxds << CTRLR0_SPI_RXDS_EN_OFFSET)
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| (inst_len << CTRLR0_INST_L_OFFSET)
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| (addr_len << CTRLR0_ADDR_L_OFFSET)
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| (wait_cycles << CTRLR0_WAIT_CYCLES_OFFSET);
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}
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ospi_writel(ospi_cfg, spi_ctrlr0, val);
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ospi_cfg->rx_req = read_len;
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spi_enable(ospi_cfg);
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}
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int ospi_recv_blocking_8bit_data(ospi_flash_cfg_t *ospi_cfg, uint32_t command, uint8_t *buffer) {
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ospi_writel(ospi_cfg, data_reg, command);
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ospi_writel(ospi_cfg, ser, ospi_cfg->ser);
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ospi_cfg->rx_cnt = 0;
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while (ospi_cfg->rx_cnt < ospi_cfg->rx_req) {
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unsigned int timeout = 100000;
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while (ospi_readl(ospi_cfg, rxflr) == 0) {
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if (--timeout == 0) {
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return -OSPI_ETIMEDOUT;
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}
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}
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*buffer++ = ospi_readl(ospi_cfg, data_reg);
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ospi_cfg->rx_cnt++;
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}
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return 0;
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}
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int ospi_recv_blocking_16bit_data(ospi_flash_cfg_t *ospi_cfg, uint32_t command, uint16_t *buffer) {
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ospi_writel(ospi_cfg, data_reg, command);
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ospi_writel(ospi_cfg, ser, ospi_cfg->ser);
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ospi_cfg->rx_cnt = 0;
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while (ospi_cfg->rx_cnt < ospi_cfg->rx_req) {
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unsigned int timeout = 100000;
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while (ospi_readl(ospi_cfg, rxflr) == 0) {
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if (--timeout == 0) {
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return -OSPI_ETIMEDOUT;
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}
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}
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*buffer++ = ospi_readl(ospi_cfg, data_reg);
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ospi_cfg->rx_cnt++;
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}
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return 0;
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}
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int ospi_recv_blocking_32bit_data(ospi_flash_cfg_t *ospi_cfg, uint32_t command, uint32_t *buffer) {
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ospi_writel(ospi_cfg, data_reg, command);
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ospi_writel(ospi_cfg, ser, ospi_cfg->ser);
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ospi_cfg->rx_cnt = 0;
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while (ospi_cfg->rx_cnt < ospi_cfg->rx_req) {
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unsigned int timeout = 100000;
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while (ospi_readl(ospi_cfg, rxflr) == 0) {
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if (--timeout == 0) {
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return -OSPI_ETIMEDOUT;
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}
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}
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*buffer++ = __ROR(ospi_readl(ospi_cfg, data_reg), 16);
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ospi_cfg->rx_cnt++;
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}
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return 0;
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}
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void ospi_setup_write_ext(ospi_flash_cfg_t *ospi_cfg, bool rxds, uint32_t inst_len, uint32_t addr_len, uint32_t data_len) {
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ospi_writel(ospi_cfg, ser, 0);
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spi_disable(ospi_cfg);
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uint32_t val = CTRLR0_IS_MST
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| (OCTAL << CTRLR0_SPI_FRF_OFFSET)
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| (TMOD_TO << CTRLR0_TMOD_OFFSET)
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| (data_len << CTRLR0_DFS_OFFSET);
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ospi_writel(ospi_cfg, ctrlr0, val);
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ospi_writel(ospi_cfg, ctrlr1, 0);
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if (ospi_cfg->ddr_en) {
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val = TRANS_TYPE_FRF_DEFINED
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| (rxds << CTRLR0_SPI_RXDS_EN_OFFSET)
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| (1 << CTRLR0_SPI_DDR_EN_OFFSET)
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| (inst_len << CTRLR0_INST_L_OFFSET)
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| (addr_len << CTRLR0_ADDR_L_OFFSET)
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| (0 << CTRLR0_WAIT_CYCLES_OFFSET);
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if (inst_len == OSPI_INST_L_16bit) {
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val |= 1 << CTRLR0_INST_DDR_EN_OFFSET;
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}
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} else {
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val = TRANS_TYPE_FRF_DEFINED
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| (rxds << CTRLR0_SPI_RXDS_EN_OFFSET)
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| (inst_len << CTRLR0_INST_L_OFFSET)
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| (addr_len << CTRLR0_ADDR_L_OFFSET)
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| (0 << CTRLR0_WAIT_CYCLES_OFFSET);
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}
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ospi_writel(ospi_cfg, spi_ctrlr0, val);
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spi_enable(ospi_cfg);
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}
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static inline uint32_t ospi_xip_ctrlr0(uint32_t data_len) {
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return CTRLR0_IS_MST
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| (OCTAL << CTRLR0_SPI_FRF_OFFSET)
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| (0 << CTRLR0_SCPOL_OFFSET)
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| (0 << CTRLR0_SCPH_OFFSET)
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| (0 << CTRLR0_SSTE_OFFSET)
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| (TMOD_RO << CTRLR0_TMOD_OFFSET)
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| (data_len << CTRLR0_DFS_OFFSET);
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}
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void ospi_xip_enter_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t inst_len, uint32_t data_len, uint16_t incr_command, uint16_t wrap_command, uint16_t read_dummy_cycles) {
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spi_disable(ospi_cfg);
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ospi_writel(ospi_cfg, ctrlr0, ospi_xip_ctrlr0(data_len));
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uint32_t val = (OCTAL << XIP_CTRL_FRF_OFFSET)
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| (0x2 << XIP_CTRL_TRANS_TYPE_OFFSET)
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| (ADDR_L32bit << XIP_CTRL_ADDR_L_OFFSET)
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| (inst_len << XIP_CTRL_INST_L_OFFSET)
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| (0x0 << XIP_CTRL_MD_BITS_EN_OFFSET)
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| (read_dummy_cycles << XIP_CTRL_WAIT_CYCLES_OFFSET)
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| (0x1 << XIP_CTRL_DFC_HC_OFFSET)
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| (ospi_cfg->ddr_en << XIP_CTRL_DDR_EN_OFFSET)
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| (0x1 << XIP_CTRL_RXDS_EN_OFFSET)
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| (0x1 << XIP_CTRL_INST_EN_OFFSET)
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| (0x1 << XIP_CTRL_CONT_XFER_EN_OFFSET)
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| (0x0 << XIP_CTRL_HYPERBUS_EN_OFFSET)
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| (0x1 << XIP_CTRL_RXDS_SIG_EN)
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| (0x0 << XIP_CTRL_XIP_MBL_OFFSET)
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| (0x0 << XIP_PREFETCH_EN_OFFSET)
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| (0x0 << XIP_CTRL_RXDS_VL_EN_OFFSET);
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if (inst_len == OSPI_INST_L_16bit) {
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val |= 1 << XIP_CTRL_INST_DDR_EN_OFFSET;
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}
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ospi_writel(ospi_cfg, xip_ctrl, val);
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ospi_writel(ospi_cfg, rx_sample_dly, OSPI_XIP_RX_SAMPLE_DELAY);
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ospi_writel(ospi_cfg, txd_drive_edge, OSPI_XIP_DDR_DRIVE_EDGE);
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ospi_cfg->aes_regs->aes_rxds_delay = OSPI_XIP_RXDS_DELAY;
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ospi_writel(ospi_cfg, xip_mode_bits, 0x0);
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ospi_writel(ospi_cfg, xip_incr_inst, incr_command);
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ospi_writel(ospi_cfg, xip_wrap_inst, wrap_command);
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ospi_writel(ospi_cfg, xip_ser, ospi_cfg->ser);
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ospi_writel(ospi_cfg, xip_cnt_time_out, 100);
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spi_enable(ospi_cfg);
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ospi_xip_enable(ospi_cfg);
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}
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void ospi_xip_exit_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t inst_len, uint16_t incr_command, uint16_t wrap_command) {
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spi_disable(ospi_cfg);
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uint32_t val = CTRLR0_IS_MST
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| (OCTAL << CTRLR0_SPI_FRF_OFFSET)
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| (0 << CTRLR0_SCPOL_OFFSET)
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| (0 << CTRLR0_SCPH_OFFSET)
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| (0 << CTRLR0_SSTE_OFFSET)
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| (TMOD_RO << CTRLR0_TMOD_OFFSET)
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| (CTRLR0_DFS_32bit << CTRLR0_DFS_OFFSET);
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ospi_writel(ospi_cfg, ctrlr0, val);
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val = TRANS_TYPE_FRF_DEFINED
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| ((ospi_cfg->ddr_en) << CTRLR0_SPI_DDR_EN_OFFSET)
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| (2 << CTRLR0_XIP_MBL_OFFSET)
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| (1 << CTRLR0_XIP_DFS_HC_OFFSET)
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| (1 << CTRLR0_XIP_INST_EN_OFFSET)
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| (inst_len << CTRLR0_INST_L_OFFSET)
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| (ospi_cfg->addrlen) << (CTRLR0_ADDR_L_OFFSET)
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| (ospi_cfg->wait_cycles << CTRLR0_WAIT_CYCLES_OFFSET);
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ospi_writel(ospi_cfg, spi_ctrlr0, val);
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ospi_writel(ospi_cfg, xip_mode_bits, 0x1);
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ospi_writel(ospi_cfg, xip_incr_inst, incr_command);
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ospi_writel(ospi_cfg, xip_wrap_inst, wrap_command);
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ospi_writel(ospi_cfg, xip_ser, ospi_cfg->ser);
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ospi_writel(ospi_cfg, ser, ospi_cfg->ser);
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ospi_writel(ospi_cfg, xip_cnt_time_out, 100);
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spi_enable(ospi_cfg);
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ospi_xip_enable(ospi_cfg);
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ospi_xip_disable(ospi_cfg);
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}
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void ospi_xip_restore_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t data_len) {
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spi_disable(ospi_cfg);
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ospi_writel(ospi_cfg, ctrlr0, ospi_xip_ctrlr0(data_len));
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spi_enable(ospi_cfg);
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}
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