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5bafb0bf68
All the existing `machine.UART` tests in extmod and extmod_hardware are converted to use the new `target_wiring` scheme, which removes a lot of duplicated board-specific settings. All the existing boards that were supported by these UART tests now have their own `target_wiring` file. Some configurations are board specific (eg NUCLEO_WB55) and others are port specific. Signed-off-by: Damien George <damien@micropython.org>
50 lines
1.3 KiB
Python
50 lines
1.3 KiB
Python
# Test machine.UART.IRQ_RXIDLE firing after a set of characters are received.
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#
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# IMPORTANT: This test requires hardware connections: the UART TX and RX
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# pins must be wired together.
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try:
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from machine import UART
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UART.IRQ_RXIDLE
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except (ImportError, AttributeError):
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print("SKIP")
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raise SystemExit
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import time, sys
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from target_wiring import uart_loopback_args, uart_loopback_kwargs
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# Target tuning options.
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tune_wait_initial_rxidle = sys.platform == "pyboard"
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def irq(u):
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print("IRQ_RXIDLE:", bool(u.irq().flags() & u.IRQ_RXIDLE), "data:", u.read())
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text = ("12345678", "abcdefgh")
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# Test that the IRQ is called for each set of byte received.
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for bits_per_s in (2400, 9600, 115200):
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print("========")
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print("bits_per_s:", bits_per_s)
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uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
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# Ignore a possible initial RXIDLE condition after creating UART.
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if tune_wait_initial_rxidle:
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uart.irq(lambda _: None, uart.IRQ_RXIDLE)
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time.sleep_ms(10)
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# Configure desired IRQ.
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uart.irq(irq, uart.IRQ_RXIDLE)
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for i in range(2):
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# Write data and wait for IRQ.
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print("write")
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uart.write(text[i])
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uart.flush()
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print("ready")
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time.sleep_ms(100)
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print("done")
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