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There are some newer PYBD_SF6 being produced which have a larger flash, namely two of 8MiB (instead of the older ones with two of 2MiB). This commit adds support for these boards. The idea is to have the same PYBD_SF6 firmware run on both old and new boards. That means autodetecting the flash at start-up and configuring all the relevant SPI/QSPI parameters, including for ROMFS and mboot. Signed-off-by: Damien George <damien@micropython.org>
122 lines
5.2 KiB
C
122 lines
5.2 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018-2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// Take PYBD_SF2 as base configuration
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#include "boards/PYBD_SF2/mpconfigboard.h"
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#undef MICROPY_HW_BOARD_NAME
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#undef MICROPY_HW_MCU_NAME
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#undef MICROPY_HW_CLK_PLLM
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#undef MICROPY_HW_CLK_PLLN
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#undef MICROPY_HW_CLK_PLLP
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#undef MICROPY_HW_CLK_PLLQ
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#undef MICROPY_HW_FLASH_LATENCY
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#define MICROPY_HW_BOARD_NAME "PYBD-SF6W"
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#define MICROPY_HW_MCU_NAME "STM32F767IIK"
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// HSE is 25MHz, run SYS at 144MHz
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#define MICROPY_HW_CLK_PLLM (25)
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#define MICROPY_HW_CLK_PLLN (288)
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#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
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#define MICROPY_HW_CLK_PLLQ (6)
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#define MICROPY_HW_FLASH_LATENCY (FLASH_LATENCY_4)
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// ROMFS config
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#define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (1)
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#define MICROPY_HW_ROMFS_QSPI_SPIFLASH_OBJ (&spi_bdev2.spiflash)
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#define MICROPY_HW_ROMFS_ENABLE_PART0 (1)
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// Extra UART config
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#define MICROPY_HW_UART7_TX (pyb_pin_W16)
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#define MICROPY_HW_UART7_RX (pyb_pin_W22B)
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// Extra CAN buses
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#define MICROPY_HW_CAN2_NAME "Y"
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#define MICROPY_HW_CAN2_TX (pyb_pin_Y6)
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#define MICROPY_HW_CAN2_RX (pyb_pin_Y5)
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// Ethernet via RMII
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#define MICROPY_HW_ETH_MDC (pyb_pin_W24)
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#define MICROPY_HW_ETH_MDIO (pyb_pin_W15)
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#define MICROPY_HW_ETH_RMII_REF_CLK (pyb_pin_W17)
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#define MICROPY_HW_ETH_RMII_CRS_DV (pyb_pin_W14)
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#define MICROPY_HW_ETH_RMII_RXD0 (pyb_pin_W51)
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#define MICROPY_HW_ETH_RMII_RXD1 (pyb_pin_W47)
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#define MICROPY_HW_ETH_RMII_TX_EN (pyb_pin_W8)
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#define MICROPY_HW_ETH_RMII_TXD0 (pyb_pin_W45)
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#define MICROPY_HW_ETH_RMII_TXD1 (pyb_pin_W49)
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// The below code reconfigures SPI flash for dynamic size detection.
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#undef MICROPY_BOARD_EARLY_INIT
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#undef MICROPY_HW_SPIFLASH_SIZE_BITS
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#undef MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2
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#undef MBOOT_SPIFLASH_BYTE_SIZE
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#undef MBOOT_SPIFLASH_LAYOUT
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#undef MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE
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#undef MBOOT_SPIFLASH2_BYTE_SIZE
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#undef MBOOT_SPIFLASH2_LAYOUT
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#undef MBOOT_SPIFLASH2_ERASE_BLOCKS_PER_PAGE
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// These are convenience macros to refer to the SPI flash chip parameters for the external SPI flash.
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#define MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0 (spi_bdev.spiflash.chip_params) // SPI flash #1, R/W storage
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#define MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1 (spi_bdev2.spiflash.chip_params) // SPI flash #2, memory mapped
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// Early init is needed to initialise the default SPI flash chip parameters.
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#define MICROPY_BOARD_EARLY_INIT board_early_init_sf6
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// Enable dynamic detection of SPI flash.
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#define MICROPY_HW_SPIFLASH_CHIP_PARAMS (1)
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#define MICROPY_HW_SPIFLASH_DETECT_DEVICE (1)
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// Settings for SPI flash #1.
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#define MICROPY_HW_SPIFLASH_SIZE_BITS (1 << (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2 + 3))
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// Settings for SPI flash #2.
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#define MICROPY_HW_QSPI_PRESCALER (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->qspi_prescaler)
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#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2 + 3)
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// ROMFS partition 0 is dynamically sized (SPI flash #2).
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#define MICROPY_HW_ROMFS_PART0_START (uintptr_t)(&_micropy_hw_romfs_part0_start)
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#define MICROPY_HW_ROMFS_PART0_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2)
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// Mboot SPI flash #1 configuration.
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#define MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN (20)
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#define MBOOT_SPIFLASH_LAYOUT (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2 == 21 ? "/0x80000000/512*4Kg" : "/0x80000000/2048*4Kg")
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#define MBOOT_SPIFLASH_BYTE_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2)
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#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
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// Mboot SPI flash #2 configuration.
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#define MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN (20)
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#define MBOOT_SPIFLASH2_LAYOUT (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2 == 21 ? "/0x90000000/512*4Kg" : "/0x90000000/2048*4Kg")
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#define MBOOT_SPIFLASH2_BYTE_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2)
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#define MBOOT_SPIFLASH2_ERASE_BLOCKS_PER_PAGE (1)
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extern unsigned char _micropy_hw_romfs_part0_start;
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void board_early_init_sf6(void);
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