stm32/boards/PYBD_SF6: Support boards with larger SPI flash.

There are some newer PYBD_SF6 being produced which have a larger flash,
namely two of 8MiB (instead of the older ones with two of 2MiB).

This commit adds support for these boards.  The idea is to have the same
PYBD_SF6 firmware run on both old and new boards.  That means autodetecting
the flash at start-up and configuring all the relevant SPI/QSPI parameters,
including for ROMFS and mboot.

Signed-off-by: Damien George <damien@micropython.org>

ports/stm32/boards/PYBD_SF6/board_init.c

@@ -1 +1,89 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdbool.h>
+#include "boardctrl.h"
+#include "qspi.h"
+
+#if BUILDING_MBOOT
+#include "mboot/mboot.h"
+#endif
+
+// Use PYBD_SF2 as base configuration.
 #include "boards/PYBD_SF2/board_init.c"
+
+// Adesto AT25SF161 16-MBit.
+static const mp_spiflash_chip_params_t chip_params_at25sf161 = {
+    .jedec_id = 0x01861f,
+    .memory_size_bytes_log2 = 21,
+    .qspi_prescaler = 3, // maximum frequency 104MHz
+    .qread_num_dummy = 2,
+};
+
+// Infineon S25FL064 64-MBit.
+static const mp_spiflash_chip_params_t chip_params_s25fl064 = {
+    .jedec_id = 0x176001,
+    .memory_size_bytes_log2 = 23,
+    .qspi_prescaler = 2, // maximum frequency 108MHz
+    .qread_num_dummy = 4,
+};
+
+// Selection of possible SPI flash chips.
+static const mp_spiflash_chip_params_t *const chip_params_table[] = {
+    &chip_params_at25sf161,
+    &chip_params_s25fl064,
+};
+
+void board_early_init_sf6(void) {
+    // Initialise default SPI flash parameters.
+    MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0 = &chip_params_at25sf161;
+    MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1 = &chip_params_at25sf161;
+
+    // Continue with standard board early init.
+    board_early_init();
+}
+
+int mp_spiflash_detect(mp_spiflash_t *spiflash, int ret, uint32_t devid) {
+    if (ret != 0) {
+        // Could not identify flash.  Succeed anyway using default chip parameters.
+        return 0;
+    }
+
+    // Try to detect the SPI flash based on the JEDEC id.
+    for (size_t i = 0; i < MP_ARRAY_SIZE(chip_params_table); ++i) {
+        if (devid == chip_params_table[i]->jedec_id) {
+            spiflash->chip_params = chip_params_table[i];
+            if (spiflash->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
+                // Reinitialise the QSPI but to set new size, prescaler and dummy bytes.
+                uint8_t num_dummy = spiflash->chip_params->qread_num_dummy;
+                spiflash->config->bus.u_qspi.proto->ioctl(spiflash->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, num_dummy);
+            }
+            break;
+        }
+    }
+
+    return 0;
+}

ports/stm32/boards/PYBD_SF6/f767.ld

@@ -18,7 +18,7 @@ MEMORY
 {
     FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K
     FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 2016K   /* sectors 1-11 3x32K 1*128K 7*256K */
-    FLASH_ROMFS (rx): ORIGIN = 0x90000000, LENGTH = 2048K   /* external QSPI */
+    FLASH_ROMFS (rx): ORIGIN = 0x90000000, LENGTH = 2048K   /* external QSPI, at least 2MiB */
     RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 512K    /* DTCM=128k, SRAM1=368K, SRAM2=16K */
 }
 
@@ -39,6 +39,5 @@ _heap_end = _sstack;
 
 /* ROMFS location */
 _micropy_hw_romfs_part0_start = ORIGIN(FLASH_ROMFS);
-_micropy_hw_romfs_part0_size = LENGTH(FLASH_ROMFS);
 
 INCLUDE common_bl.ld

ports/stm32/boards/PYBD_SF6/mpconfigboard.h

@@ -69,3 +69,53 @@
 #define MICROPY_HW_ETH_RMII_TX_EN   (pyb_pin_W8)
 #define MICROPY_HW_ETH_RMII_TXD0    (pyb_pin_W45)
 #define MICROPY_HW_ETH_RMII_TXD1    (pyb_pin_W49)
+
+// The below code reconfigures SPI flash for dynamic size detection.
+
+#undef MICROPY_BOARD_EARLY_INIT
+#undef MICROPY_HW_SPIFLASH_SIZE_BITS
+#undef MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2
+#undef MBOOT_SPIFLASH_BYTE_SIZE
+#undef MBOOT_SPIFLASH_LAYOUT
+#undef MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE
+#undef MBOOT_SPIFLASH2_BYTE_SIZE
+#undef MBOOT_SPIFLASH2_LAYOUT
+#undef MBOOT_SPIFLASH2_ERASE_BLOCKS_PER_PAGE
+
+// These are convenience macros to refer to the SPI flash chip parameters for the external SPI flash.
+#define MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0 (spi_bdev.spiflash.chip_params) // SPI flash #1, R/W storage
+#define MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1 (spi_bdev2.spiflash.chip_params) // SPI flash #2, memory mapped
+
+// Early init is needed to initialise the default SPI flash chip parameters.
+#define MICROPY_BOARD_EARLY_INIT    board_early_init_sf6
+
+// Enable dynamic detection of SPI flash.
+#define MICROPY_HW_SPIFLASH_CHIP_PARAMS (1)
+#define MICROPY_HW_SPIFLASH_DETECT_DEVICE (1)
+
+// Settings for SPI flash #1.
+#define MICROPY_HW_SPIFLASH_SIZE_BITS (1 << (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2 + 3))
+
+// Settings for SPI flash #2.
+#define MICROPY_HW_QSPI_PRESCALER   (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->qspi_prescaler)
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2 + 3)
+
+// ROMFS partition 0 is dynamically sized (SPI flash #2).
+#define MICROPY_HW_ROMFS_PART0_START (uintptr_t)(&_micropy_hw_romfs_part0_start)
+#define MICROPY_HW_ROMFS_PART0_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2)
+
+// Mboot SPI flash #1 configuration.
+#define MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN (20)
+#define MBOOT_SPIFLASH_LAYOUT       (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2 == 21 ? "/0x80000000/512*4Kg" : "/0x80000000/2048*4Kg")
+#define MBOOT_SPIFLASH_BYTE_SIZE    (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2)
+#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
+
+// Mboot SPI flash #2 configuration.
+#define MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN (20)
+#define MBOOT_SPIFLASH2_LAYOUT      (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2 == 21 ? "/0x90000000/512*4Kg" : "/0x90000000/2048*4Kg")
+#define MBOOT_SPIFLASH2_BYTE_SIZE   (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2)
+#define MBOOT_SPIFLASH2_ERASE_BLOCKS_PER_PAGE (1)
+
+extern unsigned char _micropy_hw_romfs_part0_start;
+
+void board_early_init_sf6(void);