Lerking/nanoBench
1
0
Fork 0
mirror of https://github.com/andreas-abel/nanoBench.git synced 2025-12-16 03:20:08 +01:00
Code Issues Packages Projects Releases Wiki Activity

Add ZEN3 to cpuBench.py.

Browse Source
This commit is contained in:
Bartosz Taudul
2020-11-12 23:41:35 +01:00
parent d87adcc19e
commit 210e09b7ab
1 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
tools/cpuBench/cpuBench.py
View File

@@ -54,7 +54,7 @@ serializingInstructions = {'INVD', 'INVEPT', 'INVLPG', 'INVVPID', 'LGDT', 'LIDT'
'CPUID', 'IRET', 'RSM', 'SFENCE', 'LFENCE', 'MFENCE'} 'CPUID', 'IRET', 'RSM', 'SFENCE', 'LFENCE', 'MFENCE'}
def isAMDCPU(): def isAMDCPU():
return arch in ['ZEN+', 'ZEN2'] return arch in ['ZEN+', 'ZEN2', 'ZEN3']
def isIntelCPU(): def isIntelCPU():
return not isAMDCPU() return not isAMDCPU()
@@ -247,7 +247,7 @@ def getEventConfig(event):
if arch in ['CON', 'WOL']: return 'A0.00' # RS_UOPS_DISPATCHED if arch in ['CON', 'WOL']: return 'A0.00' # RS_UOPS_DISPATCHED
if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW']: return 'C2.01' # UOPS_RETIRED.ALL if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW']: return 'C2.01' # UOPS_RETIRED.ALL
if arch in ['SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX']: return 'B1.01' # UOPS_EXECUTED.THREAD if arch in ['SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX']: return 'B1.01' # UOPS_EXECUTED.THREAD
if arch in ['ZEN+', 'ZEN2']: return '0C1.00' if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '0C1.00'
if event == 'RETIRE_SLOTS': if event == 'RETIRE_SLOTS':
if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX']: return 'C2.02' if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX']: return 'C2.02'
if event == 'UOPS_MITE': if event == 'UOPS_MITE':
@@ -296,19 +296,19 @@ def getEventConfig(event):
if event == 'DIV_CYCLES': if event == 'DIV_CYCLES':
if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'CLX']: return '14.01.CMSK=1' # undocumented on HSW, but seems to work if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'CLX']: return '14.01.CMSK=1' # undocumented on HSW, but seems to work
if arch in ['ICL']: return '14.09.CMSK=1' if arch in ['ICL']: return '14.09.CMSK=1'
if arch in ['ZEN+', 'ZEN2']: return '0D3.00' if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '0D3.00'
if event == 'ILD_STALL.LCP': if event == 'ILD_STALL.LCP':
if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX']: return '87.01' if arch in ['NHM', 'WSM', 'SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX']: return '87.01'
if event == 'INST_DECODED.DEC0': if event == 'INST_DECODED.DEC0':
if arch in ['NHM', 'WSM']: return '18.01' if arch in ['NHM', 'WSM']: return '18.01'
if event == 'FpuPipeAssignment.Total0': if event == 'FpuPipeAssignment.Total0':
if arch in ['ZEN+', 'ZEN2']: return '000.01' if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '000.01'
if event == 'FpuPipeAssignment.Total1': if event == 'FpuPipeAssignment.Total1':
if arch in ['ZEN+', 'ZEN2']: return '000.02' if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '000.02'
if event == 'FpuPipeAssignment.Total2': if event == 'FpuPipeAssignment.Total2':
if arch in ['ZEN+', 'ZEN2']: return '000.04' if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '000.04'
if event == 'FpuPipeAssignment.Total3': if event == 'FpuPipeAssignment.Total3':
if arch in ['ZEN+', 'ZEN2']: return '000.08' if arch in ['ZEN+', 'ZEN2', 'ZEN3']: return '000.08'
return None return None
@@ -1731,7 +1731,7 @@ def getChainInstrForVectorRegs(instrNode, startReg, targetReg, cRep, cType):
# We use (V)SHUFPD instead of (V)MOV*PD because the latter is a 0-latency operation on some CPUs in some cases # We use (V)SHUFPD instead of (V)MOV*PD because the latter is a 0-latency operation on some CPUs in some cases
if cType == 'FP': if cType == 'FP':
if isAVXInstr(instrNode): if isAVXInstr(instrNode):
if arch in ['ZEN+', 'ZEN2']: if arch in ['ZEN+', 'ZEN2', 'ZEN3']:
# on ZEN, all shuffles are integer operations # on ZEN, all shuffles are integer operations
chainInstrFP = 'VANDPD {0}, {1}, {1};'.format(targetReg, startReg) chainInstrFP = 'VANDPD {0}, {1}, {1};'.format(targetReg, startReg)
chainInstrFP += 'VANDPD {0}, {0}, {0};'.format(targetReg) * cRep chainInstrFP += 'VANDPD {0}, {0}, {0};'.format(targetReg) * cRep
@@ -1741,7 +1741,7 @@ def getChainInstrForVectorRegs(instrNode, startReg, targetReg, cRep, cType):
chainInstrFP += 'VSHUFPD {0}, {0}, {0}, 0;'.format(targetReg) * cRep chainInstrFP += 'VSHUFPD {0}, {0}, {0}, 0;'.format(targetReg) * cRep
chainLatencyFP = basicLatency['VSHUFPD'] * (cRep+1) chainLatencyFP = basicLatency['VSHUFPD'] * (cRep+1)
else: else:
if arch in ['ZEN+', 'ZEN2']: if arch in ['ZEN+', 'ZEN2', 'ZEN3']:
# on ZEN, all shuffles are integer operations # on ZEN, all shuffles are integer operations
chainInstrFP = 'VANDPD {0}, {1}, {1};'.format(targetReg, startReg) chainInstrFP = 'VANDPD {0}, {1}, {1};'.format(targetReg, startReg)
chainInstrFP += 'VANDPD {0}, {0}, {0};'.format(targetReg) * cRep chainInstrFP += 'VANDPD {0}, {0}, {0};'.format(targetReg) * cRep
@@ -2690,7 +2690,7 @@ def main():
resetNanoBench() resetNanoBench()
if arch in ['ZEN+', 'ZEN2']: if arch in ['ZEN+', 'ZEN2', 'ZEN3']:
configurePFCs(['UOPS','FpuPipeAssignment.Total0', 'FpuPipeAssignment.Total1', 'FpuPipeAssignment.Total2', 'FpuPipeAssignment.Total3', 'DIV_CYCLES']) configurePFCs(['UOPS','FpuPipeAssignment.Total0', 'FpuPipeAssignment.Total1', 'FpuPipeAssignment.Total2', 'FpuPipeAssignment.Total3', 'DIV_CYCLES'])
else: else:
configurePFCs(['UOPS', 'RETIRE_SLOTS', 'UOPS_MITE', 'UOPS_MS', 'UOPS_PORT0', 'UOPS_PORT1', 'UOPS_PORT2', 'UOPS_PORT3', 'UOPS_PORT4', 'UOPS_PORT5', configurePFCs(['UOPS', 'RETIRE_SLOTS', 'UOPS_MITE', 'UOPS_MS', 'UOPS_PORT0', 'UOPS_PORT1', 'UOPS_PORT2', 'UOPS_PORT3', 'UOPS_PORT4', 'UOPS_PORT5',