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Add workaround for Zen 3 L3 cache associativity.

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This commit is contained in:
Bartosz Taudul
2020-11-12 23:37:01 +01:00
parent 428b37cd51
commit d87adcc19e
1 changed files with 3 additions and 0 deletions
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3
tools/CPUID/cpuid.py
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@@ -505,6 +505,9 @@ def get_cache_info(cpu):
elif d_15_12 == 0x4: L3Assoc = 4
elif d_15_12 == 0x6: L3Assoc = 8
elif d_15_12 == 0x8: L3Assoc = 16
# Value 0x9, returned by Zen 3, is reserved according to AMD CPUID Specification document.
# The Software Optimization Guide for AMD Family 19h Processors specifies L3 cache to be 16-way associative and shared by 8 cores inside a CPU complex.
elif d_15_12 == 0x9: L3Assoc = 16
elif d_15_12 == 0xA: L3Assoc = 32
elif d_15_12 == 0xB: L3Assoc = 48
elif d_15_12 == 0xC: L3Assoc = 64