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update ZEN commits

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Andreas Abel
2019-09-06 18:23:05 +02:00
parent 894826e214
commit e39686fbf6
1 changed files with 67 additions and 46 deletions
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113
configs/cfg_Zen_all.txt
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@@ -1,5 +1,5 @@
# Performance monitoring events for AMD Family 17h processors.
# See Section 2.1.13.3 of AMD's "Preliminary Processor Programming Reference" (Apr. 2017)
# See Section 2.1.15.4 of AMD's "Processor Programming Reference" (June 2019)
000.01 FpuPipeAssignment.Total0
000.02 FpuPipeAssignment.Total1
@@ -21,28 +21,33 @@
003.20 FpRetSseAvxOps.DpMultFlops
003.40 FpRetSseAvxOps.DpDivFlops
003.80 FpRetSseAvxOps.DpMultAddFlops
004.01 FpNumMovElimScalOp.Optimized
004.02 FpNumMovElimScalOp.OptPotential
004.04 FpNumMovElimScalOp.SseMovOpsElim
004.08 FpNumMovElimScalOp.SseMovOps
004.01 FpNumMovElimScalOp.SseMovOps
004.02 FpNumMovElimScalOp.SseMovOpsElim
004.04 FpNumMovElimScalOp.OptPotential
004.08 FpNumMovElimScalOp.Optimized
005.01 FpRetiredSerOps.SseBotRet
005.02 FpRetiredSerOps.SseCtrlRet
005.04 FpRetiredSerOps.X87BotRet
005.08 FpRetiredSerOps.X87CtrlRet
025.01 LsLocks.BusLock
025.02 LsLocks.NonSpecLock
025.04 LsLocks.SpecLock
025.08 LsLocks.SpecLockMapCommit
025.00 LsLocks
026.00 LsRetClflush
027.00 LsRetCpuid
029.01 LsDispatch.LdDispatch
029.02 LsDispatch.StoreDispatch
029.04 LsDispatch.LdStDispatch
02B.00 LsSmiRx
02C.00 LsIntTaken
035.00 LsSTLF
037.01 LsStCommitCancel2.StCommitCancelWcbFull
040.00 LsDcAccesses
041.01 LsMabAllocPipe.DataPipe
041.02 LsMabAllocPipe.StPipe
041.04 LsMabAllocPipe.TlbPipeLate
041.08 LsMabAllocPipe.HwPf
041.10 LsMabAllocPipe.TlbPipeEarly
041.01 LsMabAlloc.Loads
041.02 LsMabAlloc.Stores
041.08 LsMabAlloc.DcPrefetcher
043.01 LsRefillsFromSys.MABRESP_LCL_L2
043.02 LsRefillsFromSys.LS_MABRESP_LCL_CACHE
043.08 LsRefillsFromSys.LS_MABRESP_LCL_DRAM
043.10 LsRefillsFromSys.LS_MABRESP_RMT_CACHE
043.40 LsRefillsFromSys.LS_MABRESP_RMT_DRAM
045.01 LsL1DTlbMiss.TlbReload4KL2Hit
045.02 LsL1DTlbMiss.TlbReload32KL2Hit
045.04 LsL1DTlbMiss.TlbReload2ML2Hit
@@ -51,41 +56,63 @@
045.20 LsL1DTlbMiss.TlbReload32KL2Miss
045.40 LsL1DTlbMiss.TlbReload2ML2Miss
045.80 LsL1DTlbMiss.TlbReload1GL2Miss
046.01 LsTablewalker.PerfMonTablewalkAllocDside0
046.02 LsTablewalker.PerfMonTablewalkAllocDside1
046.04 LsTablewalker.PerfMonTablewalkAllocIside0
046.08 LsTablewalker.PerfMonTablewalkAllocIside1
046.01 LsTablewalker.DcType0
046.02 LsTablewalker.DcType1
046.04 LsTablewalker.IcType0
046.08 LsTablewalker.IcType1
047.00 LsMisalAccesses
04B.01 LsPrefInstrDisp.LoadPrefetchW
04B.02 LsPrefInstrDisp.StorePrefetchW
04B.04 LsPrefInstrDisp.PrefetchNTA
052.01 LsInefSwPref.MabMchCnt
052.02 LsInefSwPref.DataPipeSwPfDcHit
04B.00 LsPrefInstrDisp
052.01 LsInefSwPref.DataPipeSwPfDcHit
052.02 LsInefSwPref.MabMchCnt
059.01 LsSwPfDcFills.MABRESP_LCL_L2
059.02 LsSwPfDcFills.LS_MABRESP_LCL_CACHE
059.08 LsSwPfDcFills.LS_MABRESP_LCL_DRAM
059.10 LsSwPfDcFills.LS_MABRESP_RMT_CACHE
059.40 LsSwPfDcFills.LS_MABRESP_RMT_DRAM
05A.01 LsHwPfDcFills.MABRESP_LCL_L2
05A.02 LsHwPfDcFills.LS_MABRESP_LCL_CACHE
05A.08 LsHwPfDcFills.LS_MABRESP_LCL_DRAM
05A.10 LsHwPfDcFills.LS_MABRESP_RMT_CACHE
05A.40 LsHwPfDcFills.LS_MABRESP_RMT_DRAM
05B.01 LsTwDcFills.MABRESP_LCL_L2
05B.02 LsTwDcFills.LS_MABRESP_LCL_CACHE
05B.08 LsTwDcFills.LS_MABRESP_LCL_DRAM
05B.10 LsTwDcFills.LS_MABRESP_RMT_CACHE
05B.40 LsTwDcFills.LS_MABRESP_RMT_DRAM
076.00 LsNotHaltedCyc
078.00 LsTlbFlush
080.00 IcFw32
081.00 IcFw32Miss
082.00 IcCacheFillL2
083.00 IcCacheFillSys
084.00 BpL1TlbMissL2Hit
085.00 BpL1TlbMissL2Miss
086.00 BpSnpReSync
087.01 IcFetchStall.IcStallBackPressure
087.02 IcFetchStall.IcStallDqEmpty
087.04 IcFetchStall.IcStallAny
08A.00 BpL1BTBCorrect
08B.00 BpL2BTBCorrect
08C.01 IcCacheInval.FillInvalidated.
08C.01 IcCacheInval.FillInvalidated
08C.02 IcCacheInval.L2InvalidatingProbe
08E.00 BpDynIndPred
091.00 BpDeReDirect
099.00 BpTlbRel
28A.01 IcOcModeSwitch.IcOcModeSwitch
28A.02 IcOcModeSwitch.OcIcModeSwitch
0AF.01 DeDisDispatchTokenStalls0.ALSQ1TokenStall
0AF.02 DeDisDispatchTokenStalls0.ALSQ2TokenStall
0AF.04 DeDisDispatchTokenStalls0.ALSQ3TokenStall
0AF.08 DeDisDispatchTokenStalls0.ALSQ3_0_TokenStall
0AF.10 DeDisDispatchTokenStalls0.ALUTokenStall
0AF.20 DeDisDispatchTokenStalls0.AGSQTokenStall
0AF.40 DeDisDispatchTokenStalls0.RetireTokenStall
0AA.01 DeDisUopsFromDecoder.DecoderDispatched
0AA.02 DeDisUopsFromDecoder.OpCacheDispatched
0AE.01 DeDisDispatchTokenStalls1.IntPhyRegFileRsrcStall
0AE.02 DeDisDispatchTokenStalls1.LoadQueueRsrcStall
0AE.04 DeDisDispatchTokenStalls1.StoreQueueRsrcStall
0AE.08 DeDisDispatchTokenStalls1.IntSchedulerMiscRsrcStall
0AE.10 DeDisDispatchTokenStalls1.TakenBrnchBufferRsrc
0AE.20 DeDisDispatchTokenStalls1.FpRegFileRsrcStall
0AE.40 DeDisDispatchTokenStalls1.FPSchRsrcStall
0AE.80 DeDisDispatchTokenStalls1.FPMiscRsrcStall
0AF.01 DeDisDispatchTokenStalls0.ALSQ1RsrcStall
0AF.02 DeDisDispatchTokenStalls0.ALSQ2RsrcStall
0AF.04 DeDisDispatchTokenStalls0.ALSQ3RsrcStall
0AF.08 DeDisDispatchTokenStalls0.ALSQ3_0_RsrcStall
0AF.10 DeDisDispatchTokenStalls0.ALURsrcStall
0AF.20 DeDisDispatchTokenStalls0.AGSQRsrcStall
0AF.40 DeDisDispatchTokenStalls0.RetireRsrcStall
0C0.00 ExRetInstr
0C1.00 ExRetCops
0C2.00 ExRetBrn
@@ -93,7 +120,6 @@
0C4.00 ExRetBrnTkn
0C5.00 ExRetBrnTknMisp
0C6.00 ExRetBrnFar
0C7.00 ExRetBrnResync
0C8.00 ExRetNearRet
0C9.00 ExRetNearRetMispred
0CA.00 ExRetBrnIndMisp
@@ -101,13 +127,12 @@
0CB.02 ExRetMmxFpInstr.MmxInstr
0CB.04 ExRetMmxFpInstr.SseInstr
0D1.00 ExRetCond
0D2.00 ExRetCondMisp
0D3.00 ExDivBusy
0D4.00 ExDivCount
1CF.01 ExTaggedIbsOps.IbsTaggedOps
1CF.02 ExTaggedIbsOps.IbsTaggedOpsRet
1CF.04 ExTaggedIbsOps.IbsCountRollover
1D0.00 IbsCountRollover
1D0.00 ExRetFusBrnchInst
060.01 L2RequestG1.OtherRequests
060.02 L2RequestG1.L2HwPf
060.04 L2RequestG1.PrefetchL2
@@ -125,13 +150,6 @@
061.40 L2RequestG2.LsRdSized
061.80 L2RequestG2.Group1
062.01 L2Latency.L2CyclesWaitingOnFills
063.01 L2WbcReq.CLZero
063.02 L2WbcReq.LocalIcClr
063.04 L2WbcReq.ZeroByteStore
063.08 L2WbcReq.I_LineFlush
063.10 L2WbcReq.CacheLineFlush
063.20 L2WbcReq.WcbClose
063.40 L2WbcReq.WcbWrite
064.01 L2CacheReqStat.IcFillMiss
064.02 L2CacheReqStat.IcFillHitS
064.04 L2CacheReqStat.IcFillHitX
@@ -140,4 +158,7 @@
064.20 L2CacheReqStat.LsRdBlkLHitS
064.40 L2CacheReqStat.LsRdBlkLHitX
064.80 L2CacheReqStat.LsRdBlkCS
06D.01 L2FillPending.L2FillBusy
06D.01 L2FillPending.L2FillBusy
070.00 L2PfHitL2
071.00 L2PfMissL2HitL3
072.00 L2PfMissL2L3