Merge pull request #101 from RRZE-HPC/feat/m1

Feat/m1

README.rst

@@ -101,7 +101,7 @@ The usage of OSACA can be listed as:
 --arch ARCH
   needs to be replaced with the target architecture abbreviation.
   Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures.
-  Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110,  and ``A64FX`` for Fujitsu's HPC ARM architecture are available.
+  Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, and ``M1`` for the Apple M1-Firestorm performance core are available.
   If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64.
 --fixed
   Run the throughput analysis with fixed port utilization for all suitable ports per instruction.

osaca/data/isa/aarch64.yml

@@ -850,7 +850,7 @@ instruction_forms:
           shape: "*"
           source: true
           destination: false
-    - name: ldp
+    - name: [ldp, ldnp]
       operands:
         - class: register
           prefix: "*"
@@ -895,7 +895,7 @@ instruction_forms:
         source: true
         destination: false
       operation: "op1['name'] = op2['name']; op1['value'] = op2['value']"
-    - name: stp
+    - name: [stp, stnp]
       operands:
         - class: register
           prefix: "*"

osaca/osaca.py

@@ -38,6 +38,7 @@ SUPPORTED_ARCHS = [
     "A64FX",
     "TSV110",
     "A72",
+    "M1",
 ]
 DEFAULT_ARCHS = {
     "aarch64": "A64FX",
@@ -101,7 +102,7 @@ def create_parser(parser=None):
         "--arch",
         type=str,
         help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, "
-        "A64FX, TSV110, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
+        "A64FX, TSV110, A72, M1). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
     )
     parser.add_argument(
         "--fixed",

osaca/parser/parser_AArch64.py

@@ -382,7 +382,7 @@ class ParserAArch64(BaseParser):
         ):
             # resolve ranges and lists
             return self.resolve_range_list(self.process_register_list(operand[self.REGISTER_ID]))
-        if self.REGISTER_ID in operand and operand[self.REGISTER_ID]["name"] == "sp":
+        if self.REGISTER_ID in operand and operand[self.REGISTER_ID]["name"].lower() == "sp":
             return self.process_sp_register(operand[self.REGISTER_ID])
         # add value attribute to floating point immediates without exponent
         if self.IMMEDIATE_ID in operand:
@@ -404,9 +404,13 @@ class ParserAArch64(BaseParser):
         base = memory_address.get("base", None)
         index = memory_address.get("index", None)
         scale = 1
-        if base is not None and "name" in base and base["name"] == "sp":
+        if base is not None and "name" in base and base["name"].lower() == "sp":
             base["prefix"] = "x"
-        if index is not None and "name" in index and index["name"] == "sp":
+        if index is not None and "name" in index and index["name"].lower() == "sp":
+            index["prefix"] = "x"
+        if base is not None and "name" in base and base["name"].lower() == "zr":
+            base["prefix"] = "x"
+        if index is not None and "name" in index and index["name"].lower() == "zr":
             index["prefix"] = "x"
         valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"]
         if "index" in memory_address:

osaca/semantics/hw_model.py

@@ -281,6 +281,7 @@ class MachineModel(object):
             "a72": "aarch64",
             "tx2": "aarch64",
             "n1": "aarch64",
+            "m1": "aarch64",
             "zen1": "x86",
             "zen+": "x86",
             "zen2": "x86",
@@ -589,7 +590,7 @@ class MachineModel(object):
             return i_operand["class"] == "prfop"
         # condition
         if "condition" in operand:
-            if i_operand["ccode"] == self.WILDCARD:
+            if i_operand["class"] == "condition" and i_operand["ccode"] == self.WILDCARD:
                 return True
             return i_operand["class"] == "condition" and (
                 operand.get("condition", None) == i_operand.get("ccode", None).upper()