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https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 10:40:06 +01:00
fixed bug in read-out of default store TP
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@@ -15,6 +15,7 @@ class MemoryOperand(Operand):
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pre_indexed=False,
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post_indexed=False,
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indexed_val=None,
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src=None,
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dst=None,
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source=False,
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destination=False,
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@@ -29,6 +30,8 @@ class MemoryOperand(Operand):
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self._pre_indexed = pre_indexed
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self._post_indexed = post_indexed
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self._indexed_val = indexed_val
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# type of register we store from (`src`) or load to (`dst`)
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self._src = src
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self._dst = dst
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@property
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@@ -71,6 +74,14 @@ class MemoryOperand(Operand):
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def indexed_val(self):
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return self._indexed_val
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@property
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def src(self):
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return self._src
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@src.setter
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def src(self, src):
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self._src = src
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@property
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def dst(self):
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return self._dst
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@@ -179,6 +179,7 @@ class MachineModel(object):
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offset=m["offset"],
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scale=m["scale"],
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index=m["index"],
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src=m["src"] if "src" in m else None,
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),
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m["port_pressure"],
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)
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@@ -408,8 +409,8 @@ class MachineModel(object):
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st_tp = [
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tp
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for tp in st_tp
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if "src" in tp[0]
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and self._check_operands(src_reg, RegisterOperand(name=tp[0]["src"]))
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if tp[0].src is not None
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and self._check_operands(src_reg, RegisterOperand(name=tp[0].src))
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]
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if len(st_tp) > 0:
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return st_tp.copy()
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