Lerking/OSACA
1
0
Fork 0
mirror of https://github.com/RRZE-HPC/OSACA.git synced 2025-12-15 16:40:05 +01:00
Code Issues Packages Projects Releases Wiki Activity

take +- operator of offset/index in mem-addr into account

Browse Source
This commit is contained in:
JanLJL
2025-03-14 15:40:16 +01:00
committed by pleroy
parent d61330404b
commit 7930e4d704
3 changed files with 75 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
tests/test_files/kernel_x86_intel_memdep.s
View File

@@ -1,15 +1,15 @@
; Translated from kernel_x86_memdep.s
L4:
vmovsd [rax+8], xmm0
add rax, 8
vmovsd [rax+rcx*8+8], xmm0
vaddsd xmm0, xmm0, [rax]
sub rax, -8
vaddsd xmm0, xmm0, [rax-8]
dec rcx
vaddsd xmm0, xmm0, [rax+rcx*8+8]
mov rdx, rcx
vaddsd xmm0, xmm0, [rax+rdx*8+8]
vmovsd [rax+8], xmm0 # line 3 <---------------------------------+
add rax, 8 # rax=rax_orig+8 |
vmovsd [rax+rcx*8+8], xmm0 # line 5 <------------------------------------------+
vaddsd xmm0, xmm0, [rax] # depends on line 3, rax+8;[rax] == [rax+8] --------+ |
sub rax, -8 # rax=rax_orig+16 | |
vaddsd xmm0, xmm0, [rax-8] # depends on line 3, rax+16;[rax-8] == [rax+8] -----+ |
dec rcx # rcx=rcx_orig-1 |
vaddsd xmm0, xmm0, [rax+rcx*8+8] # depends on line 5, [(rax+8)+(rcx-1)*8+8] == [rax+rcx*+8] --+
mov rdx, rcx # |
vaddsd xmm0, xmm0, [rax+rdx*8+8] # depends on line 5, rcx == rdx -----------------------------+
vmulsd xmm0, xmm0, xmm1
add rax, 8
cmp rsi, rax

61
tests/test_parser_x86intel.py
View File

@@ -209,15 +209,17 @@ class TestParserX86Intel(unittest.TestCase):
self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator"))
self.assertEqual(parsed_14.mnemonic, "vaddsd")
self.assertEqual(parsed_14.operands[0],
RegisterOperand(name="XMM0"))
self.assertEqual(parsed_14.operands[1],
RegisterOperand(name="XMM0"))
self.assertEqual(parsed_14.operands[2],
MemoryOperand(base=RegisterOperand(name="RDX"),
offset=ImmediateOperand(value=8),
index=RegisterOperand(name="RAX"),
scale=8))
self.assertEqual(parsed_14.operands[0], RegisterOperand(name="XMM0"))
self.assertEqual(parsed_14.operands[1], RegisterOperand(name="XMM0"))
self.assertEqual(
parsed_14.operands[2],
MemoryOperand(
base=RegisterOperand(name="RDX"),
offset=ImmediateOperand(value=8),
index=RegisterOperand(name="RAX"),
scale=8,
),
)
def test_parse_line(self):
line_comment = "; -- Begin main"
@@ -363,21 +365,32 @@ class TestParserX86Intel(unittest.TestCase):
parsed = self.parser.parse_file(self.gs_gcc_code)
self.assertEqual(parsed[0].line_number, 1)
# Check a few lines to make sure that we produced something reasonable.
self.assertEqual(parsed[61],
InstructionForm(mnemonic="vaddsd",
operands=[RegisterOperand("XMM0"),
RegisterOperand("XMM0"),
MemoryOperand(base=RegisterOperand("RDX"),
index=RegisterOperand("RAX"),
scale=8,
offset=ImmediateOperand(value=8))],
line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]",
line_number=62))
self.assertEqual(parsed[101],
InstructionForm(directive_id=DirectiveOperand(name=".long",
parameters=["1072939201"]),
line=" .long 1072939201",
line_number=102))
self.assertEqual(
parsed[61],
InstructionForm(
mnemonic="vaddsd",
operands=[
RegisterOperand("XMM0"),
RegisterOperand("XMM0"),
MemoryOperand(
base=RegisterOperand("RDX"),
index=RegisterOperand("RAX"),
scale=8,
offset=ImmediateOperand(value=8),
),
],
line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]",
line_number=62,
),
)
self.assertEqual(
parsed[101],
InstructionForm(
directive_id=DirectiveOperand(name=".long", parameters=["1072939201"]),
line=" .long 1072939201",
line_number=102,
),
)
self.assertEqual(len(parsed), 102)
def test_normalize_imd(self):