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take +- operator of offset/index in mem-addr into account

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This commit is contained in:
JanLJL
2025-03-14 15:40:16 +01:00
committed by pleroy
parent d61330404b
commit 7930e4d704
3 changed files with 75 additions and 53 deletions
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47
osaca/parser/parser_x86intel.py
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@@ -321,9 +321,7 @@ class ParserX86Intel(ParserX86):
base = base_register.setResultsName("base") base = base_register.setResultsName("base")
displacement = pp.Group( displacement = pp.Group(
pp.Group( pp.Group(integer_number ^ identifier).setResultsName(self.immediate_id)
integer_number ^ identifier
).setResultsName(self.immediate_id)
).setResultsName("displacement") ).setResultsName("displacement")
short_indexed = index_register.setResultsName("index") short_indexed = index_register.setResultsName("index")
long_indexed = ( long_indexed = (
@@ -331,11 +329,10 @@ class ParserX86Intel(ParserX86):
+ pp.Literal("*") + pp.Literal("*")
+ scale.setResultsName("scale") + scale.setResultsName("scale")
) )
indexed = pp.Group( indexed = pp.Group(short_indexed ^ long_indexed).setResultsName("indexed")
short_indexed
^ long_indexed
).setResultsName("indexed")
operator = pp.Word("+-", exact=1) operator = pp.Word("+-", exact=1)
operator_index = pp.Word("+-", exact=1).setResultsName("operator_idx")
operator_displacement = pp.Word("+-", exact=1).setResultsName("operator_disp")
# Syntax: # Syntax:
# `base` always preceedes `indexed`. # `base` always preceedes `indexed`.
@@ -347,16 +344,24 @@ class ParserX86Intel(ParserX86):
pp.Literal("[") pp.Literal("[")
+ ( + (
base base
^ (base + operator + displacement) ^ (base + operator_displacement + displacement)
^ (base + operator + displacement + operator + indexed) ^ (base + operator_displacement + displacement + operator_index + indexed)
^ (base + operator + indexed) ^ (base + operator_index + indexed)
^ (base + operator + indexed + operator + displacement) ^ (base + operator_index + indexed + operator_displacement + displacement)
^ (displacement + operator + base) ^ (displacement + operator + base)
^ (displacement + operator + base + operator + indexed) ^ (displacement + operator + base + operator_index + indexed)
^ (displacement + operator + pp.Group(long_indexed).setResultsName("indexed")) ^ (
displacement
+ operator_index
+ pp.Group(long_indexed).setResultsName("indexed")
)
^ pp.Group(long_indexed).setResultsName("indexed") ^ pp.Group(long_indexed).setResultsName("indexed")
^ (pp.Group(long_indexed).setResultsName("indexed") + operator + displacement) ^ (
) pp.Group(long_indexed).setResultsName("indexed")
+ operator_displacement
+ displacement
)
)
+ pp.Literal("]") + pp.Literal("]")
).setResultsName("register_expression") ).setResultsName("register_expression")
@@ -373,7 +378,7 @@ class ParserX86Intel(ParserX86):
self.register.setResultsName("segment") + pp.Literal(":") + immediate self.register.setResultsName("segment") + pp.Literal(":") + immediate
^ immediate + register_expression ^ immediate + register_expression
^ register_expression ^ register_expression
^ identifier + pp.Optional(pp.Literal("+") + immediate) ^ identifier + pp.Optional(operator + immediate)
).setResultsName("address_expression") ).setResultsName("address_expression")
offset_expression = pp.Group( offset_expression = pp.Group(
@@ -665,9 +670,11 @@ class ParserX86Intel(ParserX86):
if indexed: if indexed:
index = indexed.get("index") index = indexed.get("index")
scale = int(indexed.get("scale", "1"), 0) scale = int(indexed.get("scale", "1"), 0)
displacement_op = ( if register_expression.get("operator_index") == "-":
self.process_immediate(displacement.immediate) if displacement else None scale *= -1
) displacement_op = self.process_immediate(displacement.immediate) if displacement else None
if displacement_op and register_expression.get("operator_disp") == "-":
displacement_op.value *= -1
base_op = RegisterOperand(name=base.name) if base else None base_op = RegisterOperand(name=base.name) if base else None
index_op = RegisterOperand(name=index.name) if index else None index_op = RegisterOperand(name=index.name) if index else None
new_memory = MemoryOperand( new_memory = MemoryOperand(
@@ -724,6 +731,8 @@ class ParserX86Intel(ParserX86):
if "displacement" in offset_expression if "displacement" in offset_expression
else None else None
) )
if displacement and "operator_disp" == "-":
displacement.value *= -1
identifier = self.process_identifier(offset_expression.identifier) identifier = self.process_identifier(offset_expression.identifier)
identifier.offset = displacement identifier.offset = displacement
return MemoryOperand(offset=identifier) return MemoryOperand(offset=identifier)

20
tests/test_files/kernel_x86_intel_memdep.s
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@@ -1,15 +1,15 @@
; Translated from kernel_x86_memdep.s ; Translated from kernel_x86_memdep.s
L4: L4:
vmovsd [rax+8], xmm0 vmovsd [rax+8], xmm0 # line 3 <---------------------------------+
add rax, 8 add rax, 8 # rax=rax_orig+8 |
vmovsd [rax+rcx*8+8], xmm0 vmovsd [rax+rcx*8+8], xmm0 # line 5 <------------------------------------------+
vaddsd xmm0, xmm0, [rax] vaddsd xmm0, xmm0, [rax] # depends on line 3, rax+8;[rax] == [rax+8] --------+ |
sub rax, -8 sub rax, -8 # rax=rax_orig+16 | |
vaddsd xmm0, xmm0, [rax-8] vaddsd xmm0, xmm0, [rax-8] # depends on line 3, rax+16;[rax-8] == [rax+8] -----+ |
dec rcx dec rcx # rcx=rcx_orig-1 |
vaddsd xmm0, xmm0, [rax+rcx*8+8] vaddsd xmm0, xmm0, [rax+rcx*8+8] # depends on line 5, [(rax+8)+(rcx-1)*8+8] == [rax+rcx*+8] --+
mov rdx, rcx mov rdx, rcx # |
vaddsd xmm0, xmm0, [rax+rdx*8+8] vaddsd xmm0, xmm0, [rax+rdx*8+8] # depends on line 5, rcx == rdx -----------------------------+
vmulsd xmm0, xmm0, xmm1 vmulsd xmm0, xmm0, xmm1
add rax, 8 add rax, 8
cmp rsi, rax cmp rsi, rax

61
tests/test_parser_x86intel.py
View File

@@ -209,15 +209,17 @@ class TestParserX86Intel(unittest.TestCase):
self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator")) self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator"))
self.assertEqual(parsed_14.mnemonic, "vaddsd") self.assertEqual(parsed_14.mnemonic, "vaddsd")
self.assertEqual(parsed_14.operands[0], self.assertEqual(parsed_14.operands[0], RegisterOperand(name="XMM0"))
RegisterOperand(name="XMM0")) self.assertEqual(parsed_14.operands[1], RegisterOperand(name="XMM0"))
self.assertEqual(parsed_14.operands[1], self.assertEqual(
RegisterOperand(name="XMM0")) parsed_14.operands[2],
self.assertEqual(parsed_14.operands[2], MemoryOperand(
MemoryOperand(base=RegisterOperand(name="RDX"), base=RegisterOperand(name="RDX"),
offset=ImmediateOperand(value=8), offset=ImmediateOperand(value=8),
index=RegisterOperand(name="RAX"), index=RegisterOperand(name="RAX"),
scale=8)) scale=8,
),
)
def test_parse_line(self): def test_parse_line(self):
line_comment = "; -- Begin main" line_comment = "; -- Begin main"
@@ -363,21 +365,32 @@ class TestParserX86Intel(unittest.TestCase):
parsed = self.parser.parse_file(self.gs_gcc_code) parsed = self.parser.parse_file(self.gs_gcc_code)
self.assertEqual(parsed[0].line_number, 1) self.assertEqual(parsed[0].line_number, 1)
# Check a few lines to make sure that we produced something reasonable. # Check a few lines to make sure that we produced something reasonable.
self.assertEqual(parsed[61], self.assertEqual(
InstructionForm(mnemonic="vaddsd", parsed[61],
operands=[RegisterOperand("XMM0"), InstructionForm(
RegisterOperand("XMM0"), mnemonic="vaddsd",
MemoryOperand(base=RegisterOperand("RDX"), operands=[
index=RegisterOperand("RAX"), RegisterOperand("XMM0"),
scale=8, RegisterOperand("XMM0"),
offset=ImmediateOperand(value=8))], MemoryOperand(
line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]", base=RegisterOperand("RDX"),
line_number=62)) index=RegisterOperand("RAX"),
self.assertEqual(parsed[101], scale=8,
InstructionForm(directive_id=DirectiveOperand(name=".long", offset=ImmediateOperand(value=8),
parameters=["1072939201"]), ),
line=" .long 1072939201", ],
line_number=102)) line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]",
line_number=62,
),
)
self.assertEqual(
parsed[101],
InstructionForm(
directive_id=DirectiveOperand(name=".long", parameters=["1072939201"]),
line=" .long 1072939201",
line_number=102,
),
)
self.assertEqual(len(parsed), 102) self.assertEqual(len(parsed), 102)
def test_normalize_imd(self): def test_normalize_imd(self):