mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 02:30:08 +01:00
unfified STP and LDP instructions
This commit is contained in:
JanLJL
@@ -120,23 +120,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 0.33333
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uops: ~
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- name: stp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: ~
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: 0.0
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port_pressure: ~
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throughput: ~
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uops: ~
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- name: fsub
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operands:
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- class: register
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@@ -152,23 +135,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 1.0
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uops: ~
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- name: ldp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: ~
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: true
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latency: ~
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port_pressure: ~
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throughput: ~
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uops: ~
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- name: fmul
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operands:
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- class: register
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@@ -181,23 +147,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 0.5
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uops: ~
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- name: ldp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: imd
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: ~
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port_pressure: ~
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throughput: 1.0
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uops: ~
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- name: fdiv
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operands:
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- class: register
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@@ -339,23 +288,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 0.5
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uops: ~
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- name: stp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: imd
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: 0.0
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port_pressure: ~
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throughput: ~
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uops: ~
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- name: fsqrt
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operands:
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- class: register
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@@ -383,23 +315,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 0.5
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uops: ~
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- name: stp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: imd
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: 0.0
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port_pressure: ~
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throughput: ~
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uops: ~
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- name: stur
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operands:
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- class: register
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@@ -457,23 +372,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 1.0
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uops: ~
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- name: stp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: imd
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: 0.0
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port_pressure: ~
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throughput: 1.0
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uops: ~
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- name: fadd
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operands:
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- class: register
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@@ -513,40 +411,6 @@ instruction_forms:
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port_pressure: ~
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throughput: 0.5
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uops: ~
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- name: ldp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: imd
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: ~
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port_pressure: ~
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throughput: 1.0
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uops: ~
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- name: ldp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: imd
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index: ~
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scale: 1
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pre-indexed: false
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post-indexed: false
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latency: ~
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port_pressure: ~
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throughput: ~
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uops: ~
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- name: cmp
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operands:
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- class: register
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@@ -577,6 +441,312 @@ instruction_forms:
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port_pressure: ~
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throughput: 0.5
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uops: ~
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- name: ldp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: false
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67']
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uops: 2
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- name: ldp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: true
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post-indexed: false
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: ldp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: true
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: ldp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: false
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67']]
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uops: 2
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- name: ldp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: true
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post-indexed: false
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: ldp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: true
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: ldp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: false
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67']]
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uops: 2
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- name: ldp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: true
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post-indexed: false
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: ldp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: true
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throughput: 1.0
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latency: ~
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: stp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: false
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67']
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uops: 2
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- name: stp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: true
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post-indexed: false
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: stp
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: true
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: stp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: false
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67']]
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uops: 2
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- name: stp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: true
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post-indexed: false
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: stp
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: true
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67'], [2, '012']]
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uops: 4
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- name: stp
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operands:
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- class: register
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prefix: q
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
|
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pre-indexed: false
|
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post-indexed: false
|
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throughput: 1.0
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latency: 0.0
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port_pressure: [[2, '67']]
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uops: 2
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- name: stp
|
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operands:
|
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- class: register
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prefix: q
|
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- class: register
|
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prefix: q
|
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- class: memory
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base: x
|
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offset: '*'
|
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index: '*'
|
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scale: '*'
|
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pre-indexed: true
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 0.0
|
||||
port_pressure: [[2, '67'], [2, '012']]
|
||||
uops: 4
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 0.0
|
||||
port_pressure: [[2, '67'], [2, '012']]
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uops: 4
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
@@ -617,7 +787,7 @@ instruction_forms:
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
post-indexed: true
|
||||
throughput: 0.5
|
||||
latency: 4.0
|
||||
port_pressure: [[1, '67'], [1, '012']]
|
||||
@@ -662,7 +832,7 @@ instruction_forms:
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
post-indexed: true
|
||||
throughput: 0.5
|
||||
latency: 4.0
|
||||
port_pressure: [[1, '67'], [1, '012']]
|
||||
@@ -691,7 +861,7 @@ instruction_forms:
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: true
|
||||
pre-indexed: true
|
||||
post-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 4.0
|
||||
@@ -797,7 +967,7 @@ instruction_forms:
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
post-indexed: true
|
||||
throughput: 0.5
|
||||
latency: 0.0
|
||||
port_pressure: [[1, '67'], [1, '012']]
|
||||
@@ -842,7 +1012,7 @@ instruction_forms:
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
post-indexed: true
|
||||
throughput: 0.5
|
||||
latency: 0.0
|
||||
port_pressure: [[1, '67'], [1, '012']]
|
||||
@@ -871,7 +1041,7 @@ instruction_forms:
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: true
|
||||
pre-indexed: true
|
||||
post-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 0.0
|
||||
|
||||
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