Merge pull request #84 from qcjiang/feature/tsv110

Feature/tsv110

osaca/data/isa/aarch64.yml

@@ -120,7 +120,7 @@ instruction_forms:
           post-indexed: "*"
           source: true
           destination: false
-    - name: [ldr, ldur]
+    - name: [ldr, ldur, ldrb, ldrh, ldrsb, ldrsh, ldrsw]
       operands:
         - class: register
           prefix: "*"

osaca/osaca.py

@@ -32,6 +32,7 @@ SUPPORTED_ARCHS = [
     "TX2",
     "N1",
     "A64FX",
+    "TSV110",
     "A72",
 ]
 DEFAULT_ARCHS = {
@@ -96,7 +97,7 @@ def create_parser(parser=None):
         "--arch",
         type=str,
         help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ZEN1, ZEN2, TX2, N1, "
-        "A64FX, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
+        "A64FX, TSV110, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
     )
     parser.add_argument(
         "--fixed",

osaca/parser/parser_AArch64.py

@@ -104,6 +104,7 @@ class ParserAArch64(BaseParser):
             ^ pp.CaselessLiteral("ror")
             ^ pp.CaselessLiteral("sxtw")
             ^ pp.CaselessLiteral("uxtw")
+            ^ pp.CaselessLiteral("uxtb")
             ^ pp.CaselessLiteral("mul vl")
         )
         arith_immediate = pp.Group(
@@ -384,7 +385,7 @@ class ParserAArch64(BaseParser):
             base["prefix"] = "x"
         if index is not None and "name" in index and index["name"] == "sp":
             index["prefix"] = "x"
-        valid_shift_ops = ["lsl", "uxtw", "sxtw"]
+        valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"]
         if "index" in memory_address:
             if "shift" in memory_address["index"]:
                 if memory_address["index"]["shift_op"].lower() in valid_shift_ops:

osaca/semantics/arch_semantics.py

@@ -165,11 +165,7 @@ class ArchSemantics(ISASemantics):
             instruction_data = self._machine_model.get_instruction(
                 instruction_form["instruction"], instruction_form["operands"]
             )
-            if (
-                not instruction_data
-                and self._isa == "x86"
-                and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
-            ):
+            if not instruction_data and instruction_form["instruction"][-1] in self.GAS_SUFFIXES:
                 # check for instruction without GAS suffix
                 instruction_data = self._machine_model.get_instruction(
                     instruction_form["instruction"][:-1], instruction_form["operands"]
@@ -200,7 +196,6 @@ class ArchSemantics(ISASemantics):
                     )
                     if (
                         not instruction_data_reg
-                        and self._isa == "x86"
                         and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
                     ):
                         # check for instruction without GAS suffix

osaca/semantics/hw_model.py

@@ -266,6 +266,7 @@ class MachineModel(object):
         """Return ISA for given micro-arch ``arch``."""
         arch_dict = {
             "a64fx": "aarch64",
+            "tsv110": "aarch64",
             "a72": "aarch64",
             "tx2": "aarch64",
             "n1": "aarch64",
@@ -638,6 +639,12 @@ class MachineModel(object):
             ):
                 return True
             return False
+        if "lanes" in reg:
+            if "lanes" in i_reg and (
+                reg["lanes"] == i_reg["lanes"] or self.WILDCARD in (reg["lanes"] + i_reg["lanes"])
+            ):
+                return True
+            return False
         return True
 
     def _is_x86_reg_type(self, i_reg, reg, consider_masking=False):

osaca/semantics/isa_semantics.py

@@ -55,11 +55,7 @@ class ISASemantics(object):
         isa_data = self._isa_model.get_instruction(
             instruction_form["instruction"], instruction_form["operands"]
         )
-        if (
-            isa_data is None
-            and self._isa == "x86"
-            and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
-        ):
+        if isa_data is None and instruction_form["instruction"][-1] in self.GAS_SUFFIXES:
             # Check for instruction without GAS suffix
             isa_data = self._isa_model.get_instruction(
                 instruction_form["instruction"][:-1], instruction_form["operands"]
@@ -81,7 +77,6 @@ class ISASemantics(object):
                 )
                 if (
                     isa_data_reg is None
-                    and self._isa == "x86"
                     and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
                 ):
                     # Check for instruction without GAS suffix
@@ -164,11 +159,7 @@ class ISASemantics(object):
         isa_data = self._isa_model.get_instruction(
             instruction_form["instruction"], instruction_form["operands"]
         )
-        if (
-            isa_data is None
-            and self._isa == "x86"
-            and instruction_form["instruction"][-1] in self.GAS_SUFFIXES
-        ):
+        if isa_data is None and instruction_form["instruction"][-1] in self.GAS_SUFFIXES:
             # Check for instruction without GAS suffix
             isa_data = self._isa_model.get_instruction(
                 instruction_form["instruction"][:-1], instruction_form["operands"]
@@ -192,7 +183,7 @@ class ISASemantics(object):
         for o in instruction_form.operands:
             if "pre_indexed" in o.get("memory", {}):
                 # Assuming no isa_data.operation
-                if isa_data.get("operation", None) is not None:
+                if isa_data is not None and isa_data.get("operation", None) is not None:
                     raise ValueError(
                         "ISA information for pre-indexed instruction {!r} has operation set."
                         "This is currently not supprted.".format(instruction_form.line)

osaca/semantics/marker_utils.py

@@ -138,7 +138,11 @@ def find_marked_section(
                     index_start = i + 1
                 elif comments["end"] == line.comment:
                     index_end = i
-            elif line.instruction in mov_instr and len(lines) > i + 1 and lines[i + 1].directive is not None:
+            elif (
+                line.instruction in mov_instr
+                and len(lines) > i + 1
+                and lines[i + 1].directive is not None
+            ):
                 source = line.operands[0 if not reverse else 1]
                 destination = line.operands[1 if not reverse else 0]
                 # instruction pair matches, check for operands