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add some instructions in tsv110.yml
This commit is contained in:
Qingcai Jiang
@@ -29,6 +29,182 @@ instruction_forms:
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throughput: 0.5
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latency: 0.0
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port_pressure: [[1, '12']]
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# logical instructions: and (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: and
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: and
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: ands
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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- name: ands
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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# logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: orr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: orr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: eor
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: eor
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: bic
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# logical instructions: bics (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: bics
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '12']]
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uops: 1
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# shift instructions: lsl (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: lsl
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: lsl
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# shift instructions: lsr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: lsr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: lsr
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# arithmetic instructions: add (from AArch64SchedTSV110.td and ibench)
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- name: add
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operands:
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@@ -140,6 +316,18 @@ instruction_forms:
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throughput: 0.33333
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uops: 1
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# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
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- name: subs
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '12']]
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throughput: 0.5
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uops: 1
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- name: subs
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operands:
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- class: register
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@@ -165,6 +353,154 @@ instruction_forms:
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port_pressure: [[1, '3']]
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throughput: 1.0
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uops: 1
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- name: mul
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operands:
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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latency: 7.0
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port_pressure: [[1, '4']]
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throughput: 2.5
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uops: 1
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- name: mla
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operands:
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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latency: 7.0
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port_pressure: [[1, '4']]
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throughput: 2.5
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uops: 1
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- name: mla
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operands:
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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latency: 7.0
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port_pressure: [[1, '4']]
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throughput: 2.5
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uops: 1
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# arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: mla
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operands:
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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latency: 7.0
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port_pressure: [[1, '4']]
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throughput: 2.5
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uops: 1
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- name: mla
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operands:
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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latency: 7.0
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port_pressure: [[1, '4']]
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throughput: 2.5
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uops: 1
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- name: mla
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operands:
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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latency: 7.0
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port_pressure: [[1, '4']]
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throughput: 2.5
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uops: 1
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# arithmetic instructions: neg (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
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- name: neg
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 1.0
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uops: 2
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- name: neg
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 1.0
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uops: 2
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- name: neg
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operands:
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- class: register
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prefix: v
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shape: d
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- class: register
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prefix: v
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shape: d
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 1.0
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uops: 2
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- name: neg
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operands:
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- class: register
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prefix: v
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shape: s
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- class: register
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prefix: v
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shape: s
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 1.0
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uops: 2
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- name: neg
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operands:
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- class: register
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prefix: v
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shape: h
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- class: register
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prefix: v
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shape: h
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 1.0
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uops: 2
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# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
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- name: fadd
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operands:
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@@ -558,7 +894,216 @@ instruction_forms:
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port_pressure: [1, '12']
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throughput: 0.5
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uops: 1
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# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion)
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# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
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- name: zip1
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operands:
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- class: register
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prefix: v
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shape: b
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- class: register
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prefix: v
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shape: b
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- class: register
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prefix: v
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shape: b
|
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 0.5
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uops: 2
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- name: zip1
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operands:
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- class: register
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prefix: v
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shape: h
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- class: register
|
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prefix: v
|
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shape: h
|
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- class: register
|
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prefix: v
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shape: h
|
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latency: 2.0
|
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 0.5
|
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uops: 2
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- name: zip1
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operands:
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- class: register
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prefix: v
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shape: s
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- class: register
|
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prefix: v
|
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shape: s
|
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- class: register
|
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prefix: v
|
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shape: s
|
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latency: 2.0
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port_pressure: [[1, '4'], [1, '5']]
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throughput: 0.5
|
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uops: 2
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# miscellaneous instructions: zip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
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- name: zip2
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operands:
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- class: register
|
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prefix: v
|
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shape: b
|
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- class: register
|
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prefix: v
|
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shape: b
|
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- class: register
|
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prefix: v
|
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shape: b
|
||||
latency: 2.0
|
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port_pressure: [[1, '4'], [1, '5']]
|
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throughput: 0.5
|
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uops: 2
|
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- name: zip2
|
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operands:
|
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- class: register
|
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prefix: v
|
||||
shape: h
|
||||
- class: register
|
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prefix: v
|
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shape: h
|
||||
- class: register
|
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prefix: v
|
||||
shape: h
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
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throughput: 0.5
|
||||
uops: 2
|
||||
- name: zip2
|
||||
operands:
|
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- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
# miscellaneous instructions: uzip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
||||
- name: uzip1
|
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operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
- name: uzip1
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: h
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: h
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: h
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
- name: uzip1
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
# miscellaneous instructions: uzip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
|
||||
- name: uzip2
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
- name: uzip2
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: h
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: h
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: h
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
- name: uzip2
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
latency: 2.0
|
||||
port_pressure: [[1, '4'], [1, '5']]
|
||||
throughput: 0.5
|
||||
uops: 2
|
||||
# miscellaneous instructions: scvtf (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions)
|
||||
- name: scvtf
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '45']]
|
||||
throughput: 1.0
|
||||
uops: 1
|
||||
- name: scvtf
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
latency: 3.0
|
||||
port_pressure: [[2, '45']]
|
||||
throughput: 2.0
|
||||
uops: 1
|
||||
# miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion)
|
||||
- name: fmov
|
||||
operands:
|
||||
- class: register
|
||||
@@ -570,7 +1115,7 @@ instruction_forms:
|
||||
throughput: 0.0
|
||||
uops: 0
|
||||
# memory instructions: ldur (data from AArch64SchedTSV110.td)
|
||||
- name: ldr
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: w
|
||||
|
||||
Reference in New Issue
Block a user